Tzung-Chin Chang

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-compensating delay chain for multiple-date-rate interfaces
- Patent number 7,725,755
- Issue date May 25, 2010
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Input buffer for multiple differential I/O standards
- Patent number 7,710,149
- Issue date May 4, 2010
- Altera Corporation
- Jonathan Chung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Input buffer for multiple differential I/O standards
- Patent number 7,425,844
- Issue date Sep 16, 2008
- Altera Corporation
- Jonathan Chung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for RTL modeling of a register
- Patent number 7,308,659
- Issue date Dec 11, 2007
- Altera Corporation
- Gopinath Rangan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed IO buffer using auxiliary power supply
- Patent number 7,295,040
- Issue date Nov 13, 2007
- Altera Corporation
- Khai Nguyen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
On-chip termination with calibrated driver strength
- Patent number 7,221,193
- Issue date May 22, 2007
- Altera Corporation
- Xiaobao Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for controlling on-chip termination resistance using vol...
- Patent number 7,218,155
- Issue date May 15, 2007
- Altera Corporation
- Tzung-Chin Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Input buffer for multiple differential I/O standards
- Patent number 7,215,143
- Issue date May 8, 2007
- Altera Corporation
- Jonathan Chung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DLL with adjustable phase shift using processed control signal
- Patent number 7,212,054
- Issue date May 1, 2007
- Altera Corporation
- Tzung-chin Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Loop circuitry with low-pass noise filter
- Patent number 7,205,806
- Issue date Apr 17, 2007
- Altera Corporation
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-compensating delay chain for multiple-date-rate interfaces
- Patent number 7,200,769
- Issue date Apr 3, 2007
- Altera Corporation
- Yan Chong
- G11 - INFORMATION STORAGE
Information Patent Grant
Supply voltage detection circuit
- Patent number 7,119,579
- Issue date Oct 10, 2006
- Altera Corporation
- Yan Chong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable I/O element circuit for high speed logic devices
- Patent number 7,098,690
- Issue date Aug 29, 2006
- Altera Corporation
- Khai Nguyen
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
DLL with adjustable phase shift using processed control signal
- Patent number 7,091,760
- Issue date Aug 15, 2006
- Altera Corporation
- Tzung-chin Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed IO buffer using auxiliary power supply
- Patent number 7,088,140
- Issue date Aug 8, 2006
- Altera Corporation
- Khai Nguyen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Loop circuitry with low-pass noise filter
- Patent number 7,002,384
- Issue date Feb 21, 2006
- Altera Corporation
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Over-voltage protection of integrated circuit I/O pins
- Patent number 6,970,024
- Issue date Nov 29, 2005
- Altera Corporation
- Dirk Reese
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
On/off reference voltage switch for multiple I/O standards
- Patent number 6,911,860
- Issue date Jun 28, 2005
- Altera Corporation
- Xiaobao Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Supply voltage detection circuit
- Patent number 6,870,400
- Issue date Mar 22, 2005
- Altera Corporation
- Yan Chong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Schmitt trigger circuit with adjustable trip point voltages
- Patent number 6,870,413
- Issue date Mar 22, 2005
- Altera Corporation
- Tzung-Chin Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable I/O element circuit for high speed logic devices
- Patent number 6,853,215
- Issue date Feb 8, 2005
- Altera Corporation
- Khai Nguyen
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Input buffer for multiple differential I/O standards
- Patent number 6,825,692
- Issue date Nov 30, 2004
- Altera Corporation
- Jonathan Chung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable decoder for addressing a memory
- Patent number 6,747,903
- Issue date Jun 8, 2004
- Altera Corporation
- Philip Y. Pan
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable, staged, bus hold and weak pull-up for bi-directional I/O
- Patent number 6,731,137
- Issue date May 4, 2004
- Altera Corporation
- Gopinath Rangan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit for providing clock signals with low skew
- Patent number 6,731,142
- Issue date May 4, 2004
- Altera Corporation
- Bonnie Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable I/O element circuit for high speed logic devices
- Patent number 6,686,769
- Issue date Feb 3, 2004
- Altera Corporation
- Khai Nguyen
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Supply voltage detection circuit
- Patent number 6,630,844
- Issue date Oct 7, 2003
- Altera Corporation
- Yan Chong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for providing clock signals with low skew
- Patent number 6,549,045
- Issue date Apr 15, 2003
- Altera Corporation
- Bonnie Wang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Loop circuitry with low-pass noise filter
- Publication number 20060164139
- Publication date Jul 27, 2006
- Yan Chong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Supply voltage detection circuit
- Publication number 20050253626
- Publication date Nov 17, 2005
- Yan Chong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable I/O element circuit for high speed logic devices
- Publication number 20050162187
- Publication date Jul 28, 2005
- Khai Nguyen
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE

Tzung-Chin Chang

Person

Patents Grantslast 30 patents

Self-compensating delay chain for multiple-date-rate interfaces

Input buffer for multiple differential I/O standards

Input buffer for multiple differential I/O standards

Apparatus and method for RTL modeling of a register

High speed IO buffer using auxiliary power supply

On-chip termination with calibrated driver strength

Techniques for controlling on-chip termination resistance using vol...

Input buffer for multiple differential I/O standards

DLL with adjustable phase shift using processed control signal

Loop circuitry with low-pass noise filter

Self-compensating delay chain for multiple-date-rate interfaces

Supply voltage detection circuit

Programmable I/O element circuit for high speed logic devices

DLL with adjustable phase shift using processed control signal

High speed IO buffer using auxiliary power supply

Loop circuitry with low-pass noise filter

Over-voltage protection of integrated circuit I/O pins

On/off reference voltage switch for multiple I/O standards

Supply voltage detection circuit

Schmitt trigger circuit with adjustable trip point voltages

Programmable I/O element circuit for high speed logic devices

Input buffer for multiple differential I/O standards

Configurable decoder for addressing a memory

Programmable, staged, bus hold and weak pull-up for bi-directional I/O

Circuit for providing clock signals with low skew

Programmable I/O element circuit for high speed logic devices

Supply voltage detection circuit

Circuit for providing clock signals with low skew

Patents Applicationslast 30 patents

Loop circuitry with low-pass noise filter

Supply voltage detection circuit

Programmable I/O element circuit for high speed logic devices