Udo Krautz

Person

Esslingen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Fused-multiply-add floating-point operations on 128 bit wide operands
- Patent number 10,303,438
- Issue date May 28, 2019
- International Business Machines Corporation
- Tina Babinsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RAS evaluation for circuit element
- Patent number 9,703,907
- Issue date Jul 11, 2017
- International Business Machines Corporation
- Christian Jacobi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assuring chip reliability with automatic generation of drivers and...
- Patent number 9,600,616
- Issue date Mar 21, 2017
- International Business Machines Corporation
- Eli Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RAS evaluation for circuit element
- Patent number 9,569,573
- Issue date Feb 14, 2017
- International Business Machines Corporation
- Christian Jacobi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Assuring chip reliability with automatic generation of drivers and...
- Patent number 9,483,591
- Issue date Nov 1, 2016
- International Business Machines Corporation
- Eli Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying forwarding paths in pipelines
- Patent number 9,471,327
- Issue date Oct 18, 2016
- International Business Machines Corporation
- Anand B. Arunagiri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying forwarding paths in pipelines
- Patent number 9,459,878
- Issue date Oct 4, 2016
- International Business Machines Corporation
- Anand B. Arunagiri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification of a vector execution unit design
- Patent number 9,274,791
- Issue date Mar 1, 2016
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification of a vector execution unit design
- Patent number 9,268,563
- Issue date Feb 23, 2016
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal verification of a logic design
- Patent number 8,918,747
- Issue date Dec 23, 2014
- International Business Machines Corporation
- Maarten Jokob Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for building binary decision diagrams optimally f...
- Patent number 7,949,968
- Issue date May 24, 2011
- International Business Machines Corporation
- Christian Jacobi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for formal verification of an electronic circuit...
- Patent number 7,890,903
- Issue date Feb 15, 2011
- International Business Machines Corporation
- Kai Weber
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FUSED-MULTIPLY-ADD FLOATING-POINT OPERATIONS ON 128 BIT WIDE OPERANDS
- Publication number 20180203667
- Publication date Jul 19, 2018
- International Business Machines Corporation
- Tina BABINSKY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RAS EVALUATION FOR CIRCUIT ELEMENT
- Publication number 20170116362
- Publication date Apr 27, 2017
- International Business Machines Corporation
- Christian Jacobi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFYING FORWARDING PATHS IN PIPELINES
- Publication number 20150058601
- Publication date Feb 26, 2015
- International Business Machines Corporation
- Anand B. Arunagiri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFYING FORWARDING PATHS IN PIPELINES
- Publication number 20150058604
- Publication date Feb 26, 2015
- International Business Machines Corporation
- Anand B. Arunagiri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FORMAL VERIFICATION OF A LOGIC DESIGN
- Publication number 20140195785
- Publication date Jul 10, 2014
- International Business Machines Corporation
- Maarten Jakob BOERSMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFICATION OF A VECTOR EXECUTION UNIT DESIGN
- Publication number 20140156969
- Publication date Jun 5, 2014
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFICATION OF A VECTOR EXECUTION UNIT DESIGN
- Publication number 20140136815
- Publication date May 15, 2014
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR PROVIDING DEBUGGING TOOL FOR A HARDWARE DESIGN AND DEBUG...
- Publication number 20120330637
- Publication date Dec 27, 2012
- International Business Machines Corporation
- Udo KRAUTZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR FORMAL VERIFICATION OF AN ELECTRONIC CIRCUIT...
- Publication number 20090300560
- Publication date Dec 3, 2009
- International Business Machines Corporation
- Kai Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Building Binary Decision Diagrams Optimally f...
- Publication number 20080222590
- Publication date Sep 11, 2008
- Christian Jacobi
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Fused-multiply-add floating-point operations on 128 bit wide operands

RAS evaluation for circuit element

Assuring chip reliability with automatic generation of drivers and...

RAS evaluation for circuit element

Assuring chip reliability with automatic generation of drivers and...

Verifying forwarding paths in pipelines

Verifying forwarding paths in pipelines

Verification of a vector execution unit design

Verification of a vector execution unit design

Formal verification of a logic design

Method and system for building binary decision diagrams optimally f...

Method and system for formal verification of an electronic circuit...

Patents Applicationslast 30 patents

FUSED-MULTIPLY-ADD FLOATING-POINT OPERATIONS ON 128 BIT WIDE OPERANDS

RAS EVALUATION FOR CIRCUIT ELEMENT

VERIFYING FORWARDING PATHS IN PIPELINES

VERIFYING FORWARDING PATHS IN PIPELINES

FORMAL VERIFICATION OF A LOGIC DESIGN

VERIFICATION OF A VECTOR EXECUTION UNIT DESIGN

VERIFICATION OF A VECTOR EXECUTION UNIT DESIGN

METHOD FOR PROVIDING DEBUGGING TOOL FOR A HARDWARE DESIGN AND DEBUG...

METHOD AND SYSTEM FOR FORMAL VERIFICATION OF AN ELECTRONIC CIRCUIT...

Method and System for Building Binary Decision Diagrams Optimally f...