Ugo Russo

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programming selective word lines during an erase operation in a mem...
- Patent number 12,131,028
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjustment of code rate as function of memory endurance state metric
- Patent number 11,983,067
- Issue date May 14, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Charge loss mitigation throughout memory device lifecycle by proact...
- Patent number 11,977,774
- Issue date May 7, 2024
- Micron Technology, Inc.
- Steven Michael Kientz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assemblies comprising memory cells and select gates; and methods of...
- Patent number 11,961,581
- Issue date Apr 16, 2024
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Grant
Microelectronic and semiconductor devices with a tunneling structur...
- Patent number 11,925,022
- Issue date Mar 5, 2024
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Grant
Modified read counter incrementing scheme in a memory sub-system
- Patent number 11,922,029
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial block handling in a non-volatile memory device
- Patent number 11,901,014
- Issue date Feb 13, 2024
- Micron Technology, Inc.
- Zhongguang Xu
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for determining data states of memory cells
- Patent number 11,776,633
- Issue date Oct 3, 2023
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Grant
Intervallic dynamic start voltage and program verify sampling in a...
- Patent number 11,664,079
- Issue date May 30, 2023
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Grant
Void formation in charge trap structures
- Patent number 11,569,255
- Issue date Jan 31, 2023
- Micron Technology, Inc.
- Chris M Carlson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adjustable NAND write performance
- Patent number 11,526,277
- Issue date Dec 13, 2022
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intervallic dynamic start voltage and program verify sampling in a...
- Patent number 11,462,281
- Issue date Oct 4, 2022
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Grant
Electronic apparatus with an oxide-only tunneling structure by a se...
- Patent number 11,211,399
- Issue date Dec 28, 2021
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Grant
Assemblies comprising memory cells and select gates; and methods of...
- Patent number 11,170,826
- Issue date Nov 9, 2021
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Grant
Void formation in charge trap structures
- Patent number 11,037,951
- Issue date Jun 15, 2021
- Micron Technology, Inc.
- Chris M Carlson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adjustable NAND write performance
- Patent number 10,901,622
- Issue date Jan 26, 2021
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for determining data states of memory cells
- Patent number 10,872,670
- Issue date Dec 22, 2020
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods of operating memory devices and apparatuses
- Patent number 10,658,428
- Issue date May 19, 2020
- Micron Technology, Inc.
- Ugo Russo
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Assemblies comprising memory cells and select gates
- Patent number 10,614,862
- Issue date Apr 7, 2020
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cells having a plurality of resistance variable materials
- Patent number 10,460,798
- Issue date Oct 29, 2019
- Micron Technology, Inc.
- Ugo Russo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Void formation in charge trap structures
- Patent number 10,453,855
- Issue date Oct 22, 2019
- Micron Technology, Inc.
- Chris M Carlson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming phase change memory apparatuses
- Patent number 10,128,315
- Issue date Nov 13, 2018
- Micron Technology, Inc.
- Ugo Russo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cells having a plurality of resistance variable materials
- Patent number 10,102,905
- Issue date Oct 16, 2018
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase-change memory cell implant for dummy array leakage reduction
- Patent number 9,837,604
- Issue date Dec 5, 2017
- Intel Corporation
- Lequn J. Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cells having a plurality of resistance variable materials
- Patent number 9,679,641
- Issue date Jun 13, 2017
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase change memory apparatuses
- Patent number 9,627,440
- Issue date Apr 18, 2017
- Micron Technology, Inc.
- Ugo Russo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cells, integrated devices, and methods of forming memory cells
- Patent number 9,570,677
- Issue date Feb 14, 2017
- Micron Technology, Inc.
- Andrea Redaelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase-change memory cell implant for dummy array leakage reduction
- Patent number 9,559,146
- Issue date Jan 31, 2017
- Intel Corporation
- Lequn J. Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cells having a plurality of resistance variable materials
- Patent number 9,449,683
- Issue date Sep 20, 2016
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cells, integrated devices, and methods of forming memory cells
- Patent number 9,299,930
- Issue date Mar 29, 2016
- Micron Technology, Inc.
- Andrea Redaelli
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC ADJUSTMENT OF THRESHOLD VOLTAGE OFFSETS FOR WORDLINE GROUPS
- Publication number 20240427500
- Publication date Dec 26, 2024
- Micron Technology, Inc.
- Nicola Ciocchini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SLOW CHARGE LOSS MONITOR FOR POWER UP PERFORMANCE BOOSTING
- Publication number 20240274202
- Publication date Aug 15, 2024
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Application
CHARGE LOSS MITIGATION THROUGHOUT MEMORY DEVICE LIFECYCLE BY PROACT...
- Publication number 20240241672
- Publication date Jul 18, 2024
- MICRON TECHNOLGY, INC.
- Steven Michael Kientz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC
- Publication number 20240232013
- Publication date Jul 11, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Assemblies Comprising Memory Cells and Select Gates; and Methods of...
- Publication number 20240185897
- Publication date Jun 6, 2024
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Application
WRITING USER DATA INTO STORAGE MEMORY
- Publication number 20240185926
- Publication date Jun 6, 2024
- Micron Technology, Inc.
- Huai-Yuan Tseng
- G11 - INFORMATION STORAGE
Information Patent Application
MICROELECTRONIC DEVICES WITH TUNNELING STRUCTURES HAVING PARTIAL-HE...
- Publication number 20240172443
- Publication date May 23, 2024
- Lodestar Licensing Group LLC
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Application
MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM
- Publication number 20240160359
- Publication date May 16, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEDIA MANAGEMENT SCANNING WITH UNIFIED CRITERIA TO ALLEVIATE FAST A...
- Publication number 20240161838
- Publication date May 16, 2024
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Application
PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE
- Publication number 20240145010
- Publication date May 2, 2024
- Micron Technology, Inc.
- Zhongguang Xu
- G11 - INFORMATION STORAGE
Information Patent Application
ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC
- Publication number 20240070023
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTIAL BLOCK READ VOLTAGE OFFSET
- Publication number 20240071506
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Zhongguang XU
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSIENT AND STABLE STATE READ OPERATIONS OF A MEMORY DEVICE
- Publication number 20240062829
- Publication date Feb 22, 2024
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Application
MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM
- Publication number 20230393756
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE
- Publication number 20230360704
- Publication date Nov 9, 2023
- Micron Technology, Inc.
- Zhongguang Xu
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEM...
- Publication number 20230289062
- Publication date Sep 14, 2023
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVELY PROGRAMMING RETIRED WORDLINES OF A MEMORY DEVICE
- Publication number 20230214133
- Publication date Jul 6, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHARGE LOSS MITIGATION THROUGHOUT MEMORY DEVICE LIFECYCLE BY PROACT...
- Publication number 20230195379
- Publication date Jun 22, 2023
- Micron Technology, Inc.
- Steven Michael Kientz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERVALLIC DYNAMIC START VOLTAGE AND PROGRAM VERIFY SAMPLING IN A...
- Publication number 20230005553
- Publication date Jan 5, 2023
- Micron Technology, Inc.
- Lawrence Celso Miranda
- G11 - INFORMATION STORAGE
Information Patent Application
MICROELECTRONIC AND SEMICONDUCTOR DEVICES WITH A TUNNELING STRUCTUR...
- Publication number 20220102378
- Publication date Mar 31, 2022
- Micron Technology, Inc.
- Ugo Russo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Assemblies Comprising Memory Cells and Select Gates; and Methods of...
- Publication number 20220037346
- Publication date Feb 3, 2022
- Micron Technology, Inc.
- Ugo Russo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VOID FORMATION IN CHARGE TRAP STRUCTURES
- Publication number 20210265365
- Publication date Aug 26, 2021
- Micron Technology, Inc.
- Chris M. Carlson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADJUSTABLE NAND WRITE PERFORMANCE
- Publication number 20210141530
- Publication date May 13, 2021
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR DETERMINING DATA STATES OF MEMORY CELLS
- Publication number 20210098067
- Publication date Apr 1, 2021
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC APPARATUS WITH AN OXIDE-ONLY TUNNELING STRUCTURE BY A SE...
- Publication number 20210050363
- Publication date Feb 18, 2021
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Application
ADJUSTABLE NAND WRITE PERFORMANCE
- Publication number 20200210067
- Publication date Jul 2, 2020
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Assemblies Comprising Memory Cells and Select Gates; and Methods of...
- Publication number 20200202906
- Publication date Jun 25, 2020
- Micron Technology, Inc.
- Ugo Russo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHODS FOR DETERMINING DATA STATES OF MEMORY CELLS
- Publication number 20200194084
- Publication date Jun 18, 2020
- Micron Technology, Inc.
- Ugo Russo
- G11 - INFORMATION STORAGE
Information Patent Application
VOID FORMATION IN CHARGE TRAP STRUCTURES
- Publication number 20200020703
- Publication date Jan 16, 2020
- Micron Technology, Inc.
- Chris M. Carlson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Assemblies Comprising Memory Cells and Select Gates; and Methods of...
- Publication number 20190198065
- Publication date Jun 27, 2019
- Micron Technology, Inc.
- Ugo Russo
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Programming selective word lines during an erase operation in a mem...

Adjustment of code rate as function of memory endurance state metric

Charge loss mitigation throughout memory device lifecycle by proact...

Assemblies comprising memory cells and select gates; and methods of...

Microelectronic and semiconductor devices with a tunneling structur...

Modified read counter incrementing scheme in a memory sub-system

Partial block handling in a non-volatile memory device

Apparatus and methods for determining data states of memory cells

Intervallic dynamic start voltage and program verify sampling in a...

Void formation in charge trap structures

Adjustable NAND write performance

Intervallic dynamic start voltage and program verify sampling in a...

Electronic apparatus with an oxide-only tunneling structure by a se...

Assemblies comprising memory cells and select gates; and methods of...

Void formation in charge trap structures

Adjustable NAND write performance

Methods for determining data states of memory cells

Methods of operating memory devices and apparatuses

Assemblies comprising memory cells and select gates

Memory cells having a plurality of resistance variable materials

Void formation in charge trap structures

Methods of forming phase change memory apparatuses

Memory cells having a plurality of resistance variable materials

Phase-change memory cell implant for dummy array leakage reduction

Memory cells having a plurality of resistance variable materials

Phase change memory apparatuses

Memory cells, integrated devices, and methods of forming memory cells

Phase-change memory cell implant for dummy array leakage reduction

Memory cells having a plurality of resistance variable materials

Memory cells, integrated devices, and methods of forming memory cells

Patents Applicationslast 30 patents

DYNAMIC ADJUSTMENT OF THRESHOLD VOLTAGE OFFSETS FOR WORDLINE GROUPS

SLOW CHARGE LOSS MONITOR FOR POWER UP PERFORMANCE BOOSTING

CHARGE LOSS MITIGATION THROUGHOUT MEMORY DEVICE LIFECYCLE BY PROACT...

ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC

Assemblies Comprising Memory Cells and Select Gates; and Methods of...

WRITING USER DATA INTO STORAGE MEMORY

MICROELECTRONIC DEVICES WITH TUNNELING STRUCTURES HAVING PARTIAL-HE...

MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM

MEDIA MANAGEMENT SCANNING WITH UNIFIED CRITERIA TO ALLEVIATE FAST A...

PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE

ADJUSTMENT OF CODE RATE AS FUNCTION OF MEMORY ENDURANCE STATE METRIC

PARTIAL BLOCK READ VOLTAGE OFFSET

TRANSIENT AND STABLE STATE READ OPERATIONS OF A MEMORY DEVICE

MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM

PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE

PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEM...

SELECTIVELY PROGRAMMING RETIRED WORDLINES OF A MEMORY DEVICE

CHARGE LOSS MITIGATION THROUGHOUT MEMORY DEVICE LIFECYCLE BY PROACT...

INTERVALLIC DYNAMIC START VOLTAGE AND PROGRAM VERIFY SAMPLING IN A...

MICROELECTRONIC AND SEMICONDUCTOR DEVICES WITH A TUNNELING STRUCTUR...

Assemblies Comprising Memory Cells and Select Gates; and Methods of...

VOID FORMATION IN CHARGE TRAP STRUCTURES

ADJUSTABLE NAND WRITE PERFORMANCE

APPARATUS AND METHODS FOR DETERMINING DATA STATES OF MEMORY CELLS

ELECTRONIC APPARATUS WITH AN OXIDE-ONLY TUNNELING STRUCTURE BY A SE...

ADJUSTABLE NAND WRITE PERFORMANCE

Assemblies Comprising Memory Cells and Select Gates; and Methods of...

APPARATUS AND METHODS FOR DETERMINING DATA STATES OF MEMORY CELLS

VOID FORMATION IN CHARGE TRAP STRUCTURES

Assemblies Comprising Memory Cells and Select Gates; and Methods of...