Ulrich Baur

Person

Weil In Schoenbuch, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit arrangement for test inputs
- Patent number 8,479,070
- Issue date Jul 2, 2013
- International Business Machines Corporation
- Ulrich Baur
- G01 - MEASURING TESTING
Information Patent Grant
VLSI chip test power reduction
- Patent number 6,816,990
- Issue date Nov 9, 2004
- International Business Machines Corporation
- Peilin Song
- G01 - MEASURING TESTING
Information Patent Grant
Self-test for leakage current of driver/receiver stages
- Patent number 6,774,656
- Issue date Aug 10, 2004
- International Business Machines Corporation
- Ulrich Baur
- G01 - MEASURING TESTING
Information Patent Grant
Random path delay testing methodology
- Patent number 6,728,914
- Issue date Apr 27, 2004
- Cadence Design Systems, Inc.
- Kevin William McCauley
- G01 - MEASURING TESTING
Information Patent Grant
Self-test with split, asymmetric controlled driver output stage
- Patent number 6,725,171
- Issue date Apr 20, 2004
- International Business Machines Corporation
- Ulrich Baur
- G01 - MEASURING TESTING
Information Patent Grant
Global transition scan based AC method
- Patent number 6,662,324
- Issue date Dec 9, 2003
- International Business Machines Corporation
- Franco Motika
- G01 - MEASURING TESTING
Information Patent Grant
Scan structure for improving transition fault coverage and scan dia...
- Patent number 6,490,702
- Issue date Dec 3, 2002
- International Business Machines Corporation
- Peilin Song
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Integrated Circuit Arrangement For Test Inputs
- Publication number 20110320898
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Ulrich Baur
- G01 - MEASURING TESTING
Information Patent Application
VLSI chip test power reduction
- Publication number 20030145263
- Publication date Jul 31, 2003
- International Business Machines Corporation
- Peilin Song
- G01 - MEASURING TESTING
Information Patent Application
Random path delay testing methodology
- Publication number 20020083386
- Publication date Jun 27, 2002
- International Business Machines Corporation
- Kevin William McCauley
- G01 - MEASURING TESTING
Information Patent Application
Self-test for leakage current of driver/receiver stages
- Publication number 20020079915
- Publication date Jun 27, 2002
- International Business Machines Corporation
- Ulrich Baur
- G01 - MEASURING TESTING
Information Patent Application
Self-test with split, asymmetric controlled driver output stage
- Publication number 20020078400
- Publication date Jun 20, 2002
- International Business Machines Corporation
- Ulrich Baur
- G01 - MEASURING TESTING

Ulrich Baur

Person

Patents Grantslast 30 patents

Integrated circuit arrangement for test inputs

VLSI chip test power reduction

Self-test for leakage current of driver/receiver stages

Random path delay testing methodology

Self-test with split, asymmetric controlled driver output stage

Global transition scan based AC method

Scan structure for improving transition fault coverage and scan dia...

Patents Applicationslast 30 patents

Integrated Circuit Arrangement For Test Inputs

VLSI chip test power reduction

Random path delay testing methodology

Self-test for leakage current of driver/receiver stages

Self-test with split, asymmetric controlled driver output stage