Ulrich Weiss

Person

Holzgerlingen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Low latency data transfer between clock domains operated in various...
- Patent number 8,898,503
- Issue date Nov 25, 2014
- International Business Machines Corporation
- Daniel M. Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronous clock stop in a multi nodal computer system
- Patent number 8,868,960
- Issue date Oct 21, 2014
- International Business Machines Corporation
- Tobias Bergmann
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Reusable structured hardware description language design component
- Patent number 8,332,787
- Issue date Dec 11, 2012
- International Business Machines Corporation
- Friedhelm Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder structure with midcycle latch for power reduction
- Patent number 8,086,657
- Issue date Dec 27, 2011
- International Business Machines Corporation
- Wilhelm Haller
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fault tolerant time synchronization mechanism in a scaleable multi-...
- Patent number 7,865,758
- Issue date Jan 4, 2011
- International Business Machines Corporation
- Scott Barnett Swaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for fault tolerant time synchronization mechan...
- Patent number 7,761,726
- Issue date Jul 20, 2010
- International Business Machines Corporation
- Scott Barnett Swaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal delay element, method and integrated circuit device for freq...
- Patent number 7,667,504
- Issue date Feb 23, 2010
- International Business Machines Corporation
- Florian Braun
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for fault tolerant time synchronization mechan...
- Patent number 7,487,377
- Issue date Feb 3, 2009
- International Business Machines Corporation
- Scott Barnett Swaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder structure with midcycle latch for power reduction
- Patent number 7,406,495
- Issue date Jul 29, 2008
- International Business Machines Corporation
- Wilhelm Haller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant oscillator distribution in a multi-processor server system
- Patent number 7,308,592
- Issue date Dec 11, 2007
- International Business Machines Corporation
- Dietmar Schmunkamp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Eclipz wiretest for differential clock/oscillator signals
- Patent number 7,260,494
- Issue date Aug 21, 2007
- International Business Machines Corporation
- Ulrich Weiss
- G01 - MEASURING TESTING
Information Patent Grant
System and method for synchronizing divide-by counters
- Patent number 6,989,696
- Issue date Jan 24, 2006
- International Business Machines Corporation
- Rolf Hilgendorf
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Two-stage power noise filter with on and off chip capacitors
- Patent number 6,043,724
- Issue date Mar 28, 2000
- International Business Machines Corporation
- Roland Frech
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Electrical circuit for generating pulse strings
- Patent number 5,306,959
- Issue date Apr 26, 1994
- International Business Machines Corporation
- Guenter Knauft
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power regulator with overcurrent protection
- Patent number 4,855,858
- Issue date Aug 8, 1989
- International Business Machines Corporation
- Martin Boertzel
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER

Patents Applicationslast 30 patents

Information Patent Application
LOW LATENCY DATA TRANSFER BETWEEN CLOCK DOMAINS OPERATED IN VARIOUS...
- Publication number 20140136737
- Publication date May 15, 2014
- International Business Machines Corporation
- Daniel M. Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REUSABLE STRUCTURED HARDWARE DESCRIPTION LANGUAGE DESIGN COMPONENT
- Publication number 20120117524
- Publication date May 10, 2012
- International Business Machines Corporation
- Friedhelm Kessler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONOUS CLOCK STOP IN A MULTI NODAL COMPUTER SYSTEM
- Publication number 20120005516
- Publication date Jan 5, 2012
- International Business Machines Corporation
- Tobias BERGMANN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Signal Delay Element, Method and Integrated Circuit Device for Freq...
- Publication number 20090021288
- Publication date Jan 22, 2009
- International Business Machines Corporation
- Florian Braun
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Novel Adder Structure with Midcycle Latch for Power Reduction
- Publication number 20080294706
- Publication date Nov 27, 2008
- International Business Machines Corporation
- Wilhelm Haller
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Fault Tolerant Time Synchronization Mechanism in a Scaleable Multi-...
- Publication number 20080244300
- Publication date Oct 2, 2008
- International Business Machines Corporation
- Scott Barnett Swaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Fault Tolerant Time Synchronization Mechanism in a Large...
- Publication number 20080215906
- Publication date Sep 4, 2008
- International Business Machines Corporation
- Scott Barnett Swaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Eclipz wiretest for differential clock/oscillator signals
- Publication number 20060195287
- Publication date Aug 31, 2006
- International Business Machines Corporation
- Ulrich Weiss
- G01 - MEASURING TESTING
Information Patent Application
Redundant oscillator distribution in a multi-processor server system
- Publication number 20060184814
- Publication date Aug 17, 2006
- Dietmar Schmunkamp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for fault tolerant time synchronization mechan...
- Publication number 20060179364
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Scott Barnett Swaney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Novel adder structure with midcycle latch for power reduction
- Publication number 20050138103
- Publication date Jun 23, 2005
- International Business Machines Corporation
- Wilhelm Haller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR SYNCHRONIZING DIVIDE-BY COUNTERS
- Publication number 20050104637
- Publication date May 19, 2005
- International Business Machines Corporation
- Rolf Hilgendorf
- H03 - BASIC ELECTRONIC CIRCUITRY

Ulrich Weiss

Person

Patents Grantslast 30 patents

Low latency data transfer between clock domains operated in various...

Synchronous clock stop in a multi nodal computer system

Reusable structured hardware description language design component

Adder structure with midcycle latch for power reduction

Fault tolerant time synchronization mechanism in a scaleable multi-...

Method and apparatus for fault tolerant time synchronization mechan...

Signal delay element, method and integrated circuit device for freq...

Method and apparatus for fault tolerant time synchronization mechan...

Adder structure with midcycle latch for power reduction

Redundant oscillator distribution in a multi-processor server system

Eclipz wiretest for differential clock/oscillator signals

System and method for synchronizing divide-by counters

Two-stage power noise filter with on and off chip capacitors

Electrical circuit for generating pulse strings

Power regulator with overcurrent protection

Patents Applicationslast 30 patents

LOW LATENCY DATA TRANSFER BETWEEN CLOCK DOMAINS OPERATED IN VARIOUS...

REUSABLE STRUCTURED HARDWARE DESCRIPTION LANGUAGE DESIGN COMPONENT

SYNCHRONOUS CLOCK STOP IN A MULTI NODAL COMPUTER SYSTEM

Signal Delay Element, Method and Integrated Circuit Device for Freq...

Novel Adder Structure with Midcycle Latch for Power Reduction

Fault Tolerant Time Synchronization Mechanism in a Scaleable Multi-...

Method for Fault Tolerant Time Synchronization Mechanism in a Large...

Eclipz wiretest for differential clock/oscillator signals

Redundant oscillator distribution in a multi-processor server system

Method and apparatus for fault tolerant time synchronization mechan...

Novel adder structure with midcycle latch for power reduction

SYSTEM AND METHOD FOR SYNCHRONIZING DIVIDE-BY COUNTERS