Umberto Siciliani

Person

Rubano, IT

People

Patents Grantslast 30 patents

Information Patent Grant
Memory devices for suspend and resume operations
- Patent number 12,189,993
- Issue date Jan 7, 2025
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Setting switching for single-level cells
- Patent number 12,183,407
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Umberto Siciliani
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-pass corrective programming for memory cells that store multipl...
- Patent number 12,068,034
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid parallel programming of single-level cell memory
- Patent number 12,001,336
- Issue date Jun 4, 2024
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cross-temperature compensation in non-volatile memory devices
- Patent number 11,966,289
- Issue date Apr 23, 2024
- Micron Technology, Inc.
- Andrea Giovanni Xotta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Algorithm qualifier commands
- Patent number 11,967,384
- Issue date Apr 23, 2024
- Micron Technology, Inc.
- Anna Chiara Siviero
- G11 - INFORMATION STORAGE
Information Patent Grant
Express programming using advanced cache register release in a memo...
- Patent number 11,908,523
- Issue date Feb 20, 2024
- Micron Technology, Inc.
- Walter Di Francesco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices for suspend and resume operations
- Patent number 11,907,574
- Issue date Feb 20, 2024
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache read context switching in a memory sub-system
- Patent number 11,886,346
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Giuseppe D'Eliseo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous interrupt event handling in multi-plane memory devices
- Patent number 11,842,078
- Issue date Dec 12, 2023
- Micron Technology, Inc.
- Andrea Giovanni Xotta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic chip initialization retry
- Patent number 11,740,987
- Issue date Aug 29, 2023
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices for suspend and resume operations
- Patent number 11,735,268
- Issue date Aug 22, 2023
- Micron Technology, Inc.
- Umberto Siciliani
- G11 - INFORMATION STORAGE
Information Patent Grant
Temperature readings for memory devices to reduce temperature compe...
- Patent number 11,704,047
- Issue date Jul 18, 2023
- Micron Technology, Inc.
- Agostino Macerola
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for concurrently accessing different memory...
- Patent number 11,550,717
- Issue date Jan 10, 2023
- Micron Technology, Inc.
- Tommaso Vali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory systems and memory control methods
- Patent number 11,163,572
- Issue date Nov 2, 2021
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read and program operations in a memory device
- Patent number 10,922,220
- Issue date Feb 16, 2021
- Intel Corporation
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device configuration commands
- Patent number 10,585,606
- Issue date Mar 10, 2020
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for concurrently accessing different memory...
- Patent number 10,402,319
- Issue date Sep 3, 2019
- Micron Technology, Inc.
- Tommaso Vali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device configuration commands
- Patent number 10,387,060
- Issue date Aug 20, 2019
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices for reading memory cells of different memory planes
- Patent number 10,037,809
- Issue date Jul 31, 2018
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device configuration commands
- Patent number 9,940,052
- Issue date Apr 10, 2018
- Micron Technology, Inc.
- Umberto Siciliani
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND memory addressing
- Patent number 9,881,675
- Issue date Jan 30, 2018
- Intel Corporation
- Umberto Siciliani
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices for reading memory cells of different memory planes
- Patent number 9,779,826
- Issue date Oct 3, 2017
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrently reading first and second pages of memory cells having...
- Patent number 9,754,674
- Issue date Sep 5, 2017
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrently reading first and second pages of memory cells having...
- Patent number 9,502,125
- Issue date Nov 22, 2016
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND memory addressing
- Patent number 9,502,118
- Issue date Nov 22, 2016
- Intel Corporation
- Umberto Siciliani
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
STABLE STATE ERROR-HANDLING BIN SELECTION IN MEMORY DEVICES
- Publication number 20250006292
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Taylor Alu
- G11 - INFORMATION STORAGE
Information Patent Application
HYBRID PARALLEL PROGRAMMING OF SINGLE-LEVEL CELL MEMORY
- Publication number 20240281378
- Publication date Aug 22, 2024
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALGORITHM QUALIFIER COMMANDS
- Publication number 20240265973
- Publication date Aug 8, 2024
- Micron Technology, Inc.
- Anna Chiara Siviero
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING OPERATION USING CACHE REGISTER RELEASE IN A MEMORY SUB-...
- Publication number 20240203501
- Publication date Jun 20, 2024
- Micron Technology, Inc.
- Walter Di Francesco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS-TEMPERATURE COMPENSATION IN NON-VOLATILE MEMORY DEVICES
- Publication number 20240202071
- Publication date Jun 20, 2024
- Micron Technology, Inc.
- Andrea Giovanni Xotta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES FOR SUSPEND AND RESUME OPERATIONS
- Publication number 20240143235
- Publication date May 2, 2024
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-PASS CORRECTIVE PROGRAMMING FOR MEMORY CELLS THAT STORE MULTIPL...
- Publication number 20240071510
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS-TEMPERATURE COMPENSATION IN A MEMORY SUB-SYSTEM
- Publication number 20240071427
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Andrea Giovanni Xotta
- G11 - INFORMATION STORAGE
Information Patent Application
ALGORITHM QUALIFIER COMMANDS
- Publication number 20240005996
- Publication date Jan 4, 2024
- Micron Technology, Inc.
- Anna Chiara Siviero
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS-TEMPERATURE COMPENSATION IN NON-VOLATILE MEMORY DEVICES
- Publication number 20230393936
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Andrea Giovanni Xotta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR PERFORMING SUCCESSIVE ARRAY OPERATIONS IN...
- Publication number 20230298680
- Publication date Sep 21, 2023
- Micron Technology, Inc.
- Umberto Siciliani
- G11 - INFORMATION STORAGE
Information Patent Application
SHORTENED SINGLE-LEVEL CELL MEMORY PROGRAMMING
- Publication number 20230134281
- Publication date May 4, 2023
- Micron Technology, Inc.
- Leo Raimondo
- G11 - INFORMATION STORAGE
Information Patent Application
EXPRESS PROGRAMMING USING ADVANCED CACHE REGISTER RELEASE IN A MEMO...
- Publication number 20230065421
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Walter Di Francesco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INDEPENDENT PLANE ARCHITECTURE IN A MEMORY DEVICE
- Publication number 20230059543
- Publication date Feb 23, 2023
- Micron Technology, Inc.
- Andrea Giovanni Xotta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID PARALLEL PROGRAMMING OF SINGLE-LEVEL CELL MEMORY
- Publication number 20230027820
- Publication date Jan 26, 2023
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WELL RING FOR RESISTIVE GROUND POWER DOMAIN SEGREGATION
- Publication number 20230017305
- Publication date Jan 19, 2023
- Micron Technology, Inc.
- Mattia Cichocki
- G11 - INFORMATION STORAGE
Information Patent Application
SETTING SWITCHING FOR SINGLE-LEVEL CELLS
- Publication number 20220406388
- Publication date Dec 22, 2022
- Micron Technology, Inc.
- Umberto Siciliani
- G11 - INFORMATION STORAGE
Information Patent Application
TEMPERATURE READINGS FOR MEMORY DEVICES TO REDUCE TEMPERATURE COMPE...
- Publication number 20220405002
- Publication date Dec 22, 2022
- Micron Technology, Inc.
- Agostino Macerola
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS INTERRUPT EVENT HANDLING IN MULTI-PLANE MEMORY DEVICES
- Publication number 20220405013
- Publication date Dec 22, 2022
- Micron Technology, Inc.
- Andrea Giovanni Xotta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC CHIP INITIALIZATION RETRY
- Publication number 20220405182
- Publication date Dec 22, 2022
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE READ CONTEXT SWITCHING IN A MEMORY SUB-SYSTEM
- Publication number 20220342823
- Publication date Oct 27, 2022
- Micron Technology, Inc.
- Giuseppe D'Eliseo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES FOR SUSPEND AND RESUME OPERATIONS
- Publication number 20220208273
- Publication date Jun 30, 2022
- Micron Technology, Inc.
- Umberto Siciliani
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES FOR SUSPEND AND RESUME OPERATIONS
- Publication number 20220206712
- Publication date Jun 30, 2022
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAM OPERATION EXECUTION DURING PROGRAM OPERATION SUSPEND
- Publication number 20220137856
- Publication date May 5, 2022
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Systems and Memory Control Methods
- Publication number 20220050685
- Publication date Feb 17, 2022
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY...
- Publication number 20190377675
- Publication date Dec 12, 2019
- Micron Technology, Inc.
- Tommaso Vali
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE CONFIGURATION COMMANDS
- Publication number 20190369889
- Publication date Dec 5, 2019
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ AND PROGRAM OPERATIONS IN A MEMORY DEVICE
- Publication number 20190004938
- Publication date Jan 3, 2019
- Intel Corporation
- Umberto Siciliani
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE CONFIGURATION COMMANDS
- Publication number 20180217773
- Publication date Aug 2, 2018
- Micron Technology, Inc.
- Umberto Siciliani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES FOR READING MEMORY CELLS OF DIFFERENT MEMORY PLANES
- Publication number 20180075913
- Publication date Mar 15, 2018
- Micron Technology, Inc.
- Violante Moschiano
- G11 - INFORMATION STORAGE

Umberto Siciliani

Person

Patents Grantslast 30 patents

Memory devices for suspend and resume operations

Setting switching for single-level cells

Two-pass corrective programming for memory cells that store multipl...

Hybrid parallel programming of single-level cell memory

Cross-temperature compensation in non-volatile memory devices

Algorithm qualifier commands

Express programming using advanced cache register release in a memo...

Memory devices for suspend and resume operations

Cache read context switching in a memory sub-system

Asynchronous interrupt event handling in multi-plane memory devices

Automatic chip initialization retry

Memory devices for suspend and resume operations

Temperature readings for memory devices to reduce temperature compe...

Apparatuses and methods for concurrently accessing different memory...

Memory systems and memory control methods

Read and program operations in a memory device

Memory device configuration commands

Apparatuses and methods for concurrently accessing different memory...

Memory device configuration commands

Memory devices for reading memory cells of different memory planes

Memory device configuration commands

NAND memory addressing

Memory devices for reading memory cells of different memory planes

Concurrently reading first and second pages of memory cells having...

Concurrently reading first and second pages of memory cells having...

NAND memory addressing

Patents Applicationslast 30 patents

STABLE STATE ERROR-HANDLING BIN SELECTION IN MEMORY DEVICES

HYBRID PARALLEL PROGRAMMING OF SINGLE-LEVEL CELL MEMORY

ALGORITHM QUALIFIER COMMANDS

PROGRAMMING OPERATION USING CACHE REGISTER RELEASE IN A MEMORY SUB-...

CROSS-TEMPERATURE COMPENSATION IN NON-VOLATILE MEMORY DEVICES

MEMORY DEVICES FOR SUSPEND AND RESUME OPERATIONS

TWO-PASS CORRECTIVE PROGRAMMING FOR MEMORY CELLS THAT STORE MULTIPL...

CROSS-TEMPERATURE COMPENSATION IN A MEMORY SUB-SYSTEM

ALGORITHM QUALIFIER COMMANDS

CROSS-TEMPERATURE COMPENSATION IN NON-VOLATILE MEMORY DEVICES

APPARATUS AND METHODS FOR PERFORMING SUCCESSIVE ARRAY OPERATIONS IN...

SHORTENED SINGLE-LEVEL CELL MEMORY PROGRAMMING

EXPRESS PROGRAMMING USING ADVANCED CACHE REGISTER RELEASE IN A MEMO...

INDEPENDENT PLANE ARCHITECTURE IN A MEMORY DEVICE

HYBRID PARALLEL PROGRAMMING OF SINGLE-LEVEL CELL MEMORY

WELL RING FOR RESISTIVE GROUND POWER DOMAIN SEGREGATION

SETTING SWITCHING FOR SINGLE-LEVEL CELLS

TEMPERATURE READINGS FOR MEMORY DEVICES TO REDUCE TEMPERATURE COMPE...

ASYNCHRONOUS INTERRUPT EVENT HANDLING IN MULTI-PLANE MEMORY DEVICES

AUTOMATIC CHIP INITIALIZATION RETRY

CACHE READ CONTEXT SWITCHING IN A MEMORY SUB-SYSTEM

MEMORY DEVICES FOR SUSPEND AND RESUME OPERATIONS

MEMORY DEVICES FOR SUSPEND AND RESUME OPERATIONS

PROGRAM OPERATION EXECUTION DURING PROGRAM OPERATION SUSPEND

Memory Systems and Memory Control Methods

APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY...

MEMORY DEVICE CONFIGURATION COMMANDS

READ AND PROGRAM OPERATIONS IN A MEMORY DEVICE

MEMORY DEVICE CONFIGURATION COMMANDS

MEMORY DEVICES FOR READING MEMORY CELLS OF DIFFERENT MEMORY PLANES