Usha Narasimha

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Dallas, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Generating delays of exit points for a clock circuit
- Patent number 10,203,718
- Issue date Feb 12, 2019
- Xilinx, Inc.
- Usha Narasimha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing verification in a programmable circuit design using variatio...
- Patent number 10,162,916
- Issue date Dec 25, 2018
- Xilinx, Inc.
- Usha Narasimha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-mode circuit and a method for preventing degradation in the m...
- Patent number 8,013,635
- Issue date Sep 6, 2011
- Texas Instruments Incorporated
- Palkesh Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Accurate noise modeling in digital designs
- Patent number 7,363,604
- Issue date Apr 22, 2008
- Texas Instruments Incorporated
- Anthony M. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for circuit sensitivity driven parasitic extraction
- Patent number 7,318,208
- Issue date Jan 8, 2008
- Texas Instruments Incorporated
- Usha Narasimha
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-MODE CIRCUIT AND A METHOD FOR PREVENTING DEGRADATION IN THE M...
- Publication number 20110193588
- Publication date Aug 11, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Palkesh JAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Accurate noise modeling in digital designs
- Publication number 20070079265
- Publication date Apr 5, 2007
- Anthony M. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for circuit sensitivity driven parasitic extraction
- Publication number 20060085776
- Publication date Apr 20, 2006
- Usha Narasimha
- G06 - COMPUTING CALCULATING COUNTING