Uzi Zangi

Person

Hod-Hasharon, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Ultra-low power driver of reference voltage
- Patent number 10,411,688
- Issue date Sep 10, 2019
- PLSense Ltd.
- Tuvia Liran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatuses for SW programmable adaptive bias control f...
- Patent number 10,120,967
- Issue date Nov 6, 2018
- PLSense Ltd.
- Uzi Zangi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CMOS input buffer with low supply current and voltage down shifting
- Patent number 9,935,636
- Issue date Apr 3, 2018
- PLSense Ltd.
- Tuvia Liran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatuses for adaptive dynamic voltage control for op...
- Patent number 9,935,542
- Issue date Apr 3, 2018
- PLSense Ltd.
- Uzi Zangi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
In line critical path delay measurement for accurate timing indicat...
- Patent number 9,882,564
- Issue date Jan 30, 2018
- PLSense Ltd.
- Uzi Zangi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatuses for sub-threhold clock tree design for opti...
- Patent number 9,768,775
- Issue date Sep 19, 2017
- PLSense Ltd.
- Uzi Zangi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatuses for multiple concurrent sub-threshold volta...
- Patent number 9,531,385
- Issue date Dec 27, 2016
- PLSense Ltd.
- Uzi Zangi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatuses for a network language configuration API
- Patent number 8,483,088
- Issue date Jul 9, 2013
- Siverge Networks Ltd
- Amit Margalit
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Rational Ratio Multiplier (RRM) With Optimized Duty Cycle implement...
- Publication number 20230216506
- Publication date Jul 6, 2023
- PLSENSE LTD.
- Uzi Zangi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND APPARATUSES FOR SW PROGRAMMABLE ADAPTIVE BIAS CONTROL F...
- Publication number 20160283630
- Publication date Sep 29, 2016
- PLSENSE LTD.
- Uzi Zangi
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUSES FOR ADAPTIVE DYNAMIC VOLTAGE CONTROL FOR OP...
- Publication number 20160267208
- Publication date Sep 15, 2016
- PLSENSE LTD.
- Uzi Zangi
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUSES FOR SUB-THREHOLD CLOCK TREE DESIGN FOR OPTI...
- Publication number 20160126954
- Publication date May 5, 2016
- PLSENSE LTD.
- Uzi Zangi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND APPARATUSES FOR MULTIPLE CONCURRENT SUB-THRESHOLD VOLTA...
- Publication number 20160105178
- Publication date Apr 14, 2016
- Uzi Zangi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND APPARATUSES FOR ULTRA-LOW-POWER SYSTEM ON A CHIP (SoC)...
- Publication number 20160105162
- Publication date Apr 14, 2016
- Uzi Zangi
- H03 - BASIC ELECTRONIC CIRCUITRY

Person

Patents Grantslast 30 patents

Ultra-low power driver of reference voltage

Methods and apparatuses for SW programmable adaptive bias control f...

CMOS input buffer with low supply current and voltage down shifting

Methods and apparatuses for adaptive dynamic voltage control for op...

In line critical path delay measurement for accurate timing indicat...

Methods and apparatuses for sub-threhold clock tree design for opti...

Methods and apparatuses for multiple concurrent sub-threshold volta...

Methods and apparatuses for a network language configuration API

Patents Applicationslast 30 patents

Rational Ratio Multiplier (RRM) With Optimized Duty Cycle implement...

METHODS AND APPARATUSES FOR SW PROGRAMMABLE ADAPTIVE BIAS CONTROL F...

METHODS AND APPARATUSES FOR ADAPTIVE DYNAMIC VOLTAGE CONTROL FOR OP...

METHODS AND APPARATUSES FOR SUB-THREHOLD CLOCK TREE DESIGN FOR OPTI...

METHODS AND APPARATUSES FOR MULTIPLE CONCURRENT SUB-THRESHOLD VOLTA...

METHODS AND APPARATUSES FOR ULTRA-LOW-POWER SYSTEM ON A CHIP (SoC)...