Vadali Mahadev

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for automated integrated circuit package testing
- Patent number 10,048,306
- Issue date Aug 14, 2018
- Altera Corporation
- Srikanth Darbha
- G01 - MEASURING TESTING
Information Patent Grant
Structure and assembly procedure for low stress thin die flip chip...
- Patent number 8,212,353
- Issue date Jul 3, 2012
- Altera Corporation
- Wen-chou Vincent Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and assembly procedure for low stress thin die flip chip...
- Patent number 7,741,160
- Issue date Jun 22, 2010
- Altera Corporation
- Wen-chou Vincent Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and assembly procedure for low stress thin die flip chip...
- Patent number 7,585,702
- Issue date Sep 8, 2009
- Altera Corporation
- Wen-chou Vincent Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and methods for assessing reliability of assemblies using...
- Patent number 7,210,081
- Issue date Apr 24, 2007
- Altera Corporation
- Bruce Euzent
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Systems And Methods For Circuit Design Dependent Programmable Maxim...
- Publication number 20220004688
- Publication date Jan 6, 2022
- Intel Corporation
- Archanna Srinivasan
- G06 - COMPUTING CALCULATING COUNTING