Valentin Andrei

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sparse optimizations for a matrix accelerator architecture
- Patent number 12,293,431
- Issue date May 6, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On chip dense memory for temporal buffering
- Patent number 12,254,526
- Issue date Mar 18, 2025
- Intel Corporation
- Varghese George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for synchronization of multi-thread lanes
- Patent number 12,223,353
- Issue date Feb 11, 2025
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,182,035
- Issue date Dec 31, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,124,383
- Issue date Oct 22, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar core integration
- Patent number 12,117,962
- Issue date Oct 15, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression techniques
- Patent number 12,093,210
- Issue date Sep 17, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,066,975
- Issue date Aug 20, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,056,059
- Issue date Aug 6, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management for detecting cross tile access provid...
- Patent number 11,995,029
- Issue date May 28, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic memory reconfiguration
- Patent number 11,954,062
- Issue date Apr 9, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assistance for hardware prefetch in cache access
- Patent number 11,934,342
- Issue date Mar 19, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data prefetching for graphics data processing
- Patent number 11,892,950
- Issue date Feb 6, 2024
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for exploiting queues and transitional storage...
- Patent number 11,869,113
- Issue date Jan 9, 2024
- Intel Corporation
- Aravindh Anantaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory prefetching in multiple GPU environment
- Patent number 11,861,759
- Issue date Jan 2, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for synchronization of multi-thread lanes
- Patent number 11,816,500
- Issue date Nov 14, 2023
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local memory sharing between kernels
- Patent number 11,809,905
- Issue date Nov 7, 2023
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar core integration
- Patent number 11,762,804
- Issue date Sep 19, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse optimizations for a matrix accelerator architecture
- Patent number 11,676,239
- Issue date Jun 13, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 11,620,256
- Issue date Apr 4, 2023
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics systems and methods for accelerating synchronization using...
- Patent number 11,561,828
- Issue date Jan 24, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preemptive page fault handling
- Patent number 11,416,411
- Issue date Aug 16, 2022
- Intel Corporation
- Murali Ramadoss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar core integration
- Patent number 11,409,693
- Issue date Aug 9, 2022
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data prefetching for graphics data processing
- Patent number 11,409,658
- Issue date Aug 9, 2022
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250209564
- Publication date Jun 26, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON CHIP DENSE MEMORY FOR TEMPORAL BUFFERING
- Publication number 20250200697
- Publication date Jun 19, 2025
- Intel Corporation
- Varghese George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20250173308
- Publication date May 29, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES
- Publication number 20250156222
- Publication date May 15, 2025
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250117356
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20250103546
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR CACHE OPTIMIZATION
- Publication number 20250103511
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250103547
- Publication date Mar 27, 2025
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20250068588
- Publication date Feb 27, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250004981
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20240256483
- Publication date Aug 1, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Publication number 20240256456
- Publication date Aug 1, 2024
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MEMORY RECONFIGURATION
- Publication number 20240184739
- Publication date Jun 6, 2024
- Intel Corporation
- Joydeep RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR EXPLOITING QUEUES AND TRANSITIONAL STORAGE...
- Publication number 20240169466
- Publication date May 23, 2024
- Intel Corporation
- Aravindh Anantaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT
- Publication number 20240161226
- Publication date May 16, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES
- Publication number 20240103910
- Publication date Mar 28, 2024
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...
- Publication number 20240086357
- Publication date Mar 14, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20240045830
- Publication date Feb 8, 2024
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20230351543
- Publication date Nov 2, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PREFETCHING FOR GRAPHICS DATA PROCESSING
- Publication number 20230051190
- Publication date Feb 16, 2023
- Intel Corporation
- Vikranth Vemulapalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20230029176
- Publication date Jan 26, 2023
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR CACHE OPTIMIZATION
- Publication number 20220350751
- Publication date Nov 3, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20220261347
- Publication date Aug 18, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT
- Publication number 20220222767
- Publication date Jul 14, 2022
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20220179787
- Publication date Jun 9, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...
- Publication number 20220180467
- Publication date Jun 9, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING

Valentin Andrei

Person

Patents Grantslast 30 patents

Sparse optimizations for a matrix accelerator architecture

On chip dense memory for temporal buffering

Systems and methods for synchronization of multi-thread lanes

Systems and methods for improving cache efficiency and utilization

Graphics processor data access and sharing

Multi-tile memory management

Systems and methods for cache optimization

Cache structure and utilization

Systolic disaggregation within a matrix accelerator architecture

Systems and methods for cache optimization

Scalar core integration

Multi-tile memory management

Compression techniques

Cache structure and utilization

Systems and methods for cache optimization

Multi-tile memory management for detecting cross tile access provid...

Dynamic memory reconfiguration

Assistance for hardware prefetch in cache access

Data prefetching for graphics data processing

Systems and methods for exploiting queues and transitional storage...

Memory prefetching in multiple GPU environment

Systems and methods for synchronization of multi-thread lanes

Local memory sharing between kernels

Scalar core integration

Sparse optimizations for a matrix accelerator architecture

Systems and methods for improving cache efficiency and utilization

Graphics systems and methods for accelerating synchronization using...

Preemptive page fault handling

Scalar core integration

Data prefetching for graphics data processing

Patents Applicationslast 30 patents

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE

ON CHIP DENSE MEMORY FOR TEMPORAL BUFFERING

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES

MULTI-TILE MEMORY MANAGEMENT

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

CACHE STRUCTURE AND UTILIZATION

SYSTEMS AND METHODS FOR CACHE OPTIMIZATION

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

SCALAR CORE INTEGRATION

MULTI-TILE MEMORY MANAGEMENT

CACHE STRUCTURE AND UTILIZATION

COMPRESSION TECHNIQUES

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

DYNAMIC MEMORY RECONFIGURATION

SYSTEMS AND METHODS FOR EXPLOITING QUEUES AND TRANSITIONAL STORAGE...

MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT

SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES

SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...

SCALAR CORE INTEGRATION

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE

DATA PREFETCHING FOR GRAPHICS DATA PROCESSING

SCALAR CORE INTEGRATION

SYSTEMS AND METHODS FOR CACHE OPTIMIZATION

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...