TREA

Valery Fouron

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  • Pittsburgh, PA, US
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Patents Grantslast 30 patents

  • Information Patent Grant

    Synthesis of clock gated circuit
    • Patent number 9,003,339
    • Issue date Apr 7, 2015
    • Cadence Design Systems, Inc.
    • Mark Jensen
    • G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

  • Information Patent Application

    DESIGN SYNTHESIS OF CLOCK GATED CIRCUIT
    • Publication number 20140258948
    • Publication date Sep 11, 2014
    • Cadence Design Systems, Inc.
    • Mark Jensen
    • G06 - COMPUTING CALCULATING COUNTING