Vamsee Vardhan Chivukula

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hierarchical depth buffer back annotation
- Patent number 11,615,584
- Issue date Mar 28, 2023
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous execution mechanism
- Patent number 11,494,867
- Issue date Nov 8, 2022
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low granularity coarse depth test efficiency enhancement
- Patent number 11,250,539
- Issue date Feb 15, 2022
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical depth buffer back annotation
- Patent number 11,080,925
- Issue date Aug 3, 2021
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous execution mechanism
- Patent number 10,861,126
- Issue date Dec 8, 2020
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low granularity coarse depth test efficiency enhancement
- Patent number 10,748,242
- Issue date Aug 18, 2020
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical depth buffer back annotaton
- Patent number 10,424,107
- Issue date Sep 24, 2019
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics with early stencil test
- Patent number 10,319,138
- Issue date Jun 11, 2019
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low granularity coarse depth test efficiency enhancement
- Patent number 10,102,609
- Issue date Oct 16, 2018
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DYNAMIC ROUTING OF TEXTURE LOADS IN GRAPHICS PROCESSING
- Publication number 20230101654
- Publication date Mar 30, 2023
- Intel Corporation
- Carlos Nava Rodriguez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SMALL POLYGON RASTERIZATION
- Publication number 20220383569
- Publication date Dec 1, 2022
- Intel Corporation
- Jorge Garcia Pabon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL DEPTH BUFFER BACK ANNOTATION
- Publication number 20220051473
- Publication date Feb 17, 2022
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS EXECUTION MECHANISM
- Publication number 20210256653
- Publication date Aug 19, 2021
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW GRANULARITY COARSE DEPTH TEST EFFICIENCY ENHANCEMENT
- Publication number 20210035259
- Publication date Feb 4, 2021
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYNCHRONOUS EXECUTION MECHANISM
- Publication number 20200402196
- Publication date Dec 24, 2020
- Intel Corporation
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL DEPTH BUFFER BACK ANNOTATON
- Publication number 20200098167
- Publication date Mar 26, 2020
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW GRANULARITY COARSE DEPTH TEST EFFICIENCY ENHANCEMENT
- Publication number 20190026855
- Publication date Jan 24, 2019
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS WITH EARLY STENCIL TEST
- Publication number 20180286102
- Publication date Oct 4, 2018
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW GRANULARITY COARSE DEPTH TEST EFFICIENCY ENHANCEMENT
- Publication number 20180286011
- Publication date Oct 4, 2018
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL DEPTH BUFFER BACK ANNOTATON
- Publication number 20180286113
- Publication date Oct 4, 2018
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING

Vamsee Vardhan Chivukula

Person

Patents Grantslast 30 patents

Hierarchical depth buffer back annotation

Asynchronous execution mechanism

Low granularity coarse depth test efficiency enhancement

Hierarchical depth buffer back annotation

Asynchronous execution mechanism

Low granularity coarse depth test efficiency enhancement

Hierarchical depth buffer back annotaton

Graphics with early stencil test

Low granularity coarse depth test efficiency enhancement

Patents Applicationslast 30 patents

DYNAMIC ROUTING OF TEXTURE LOADS IN GRAPHICS PROCESSING

SMALL POLYGON RASTERIZATION

HIERARCHICAL DEPTH BUFFER BACK ANNOTATION

ASYNCHRONOUS EXECUTION MECHANISM

LOW GRANULARITY COARSE DEPTH TEST EFFICIENCY ENHANCEMENT

ASYNCHRONOUS EXECUTION MECHANISM

HIERARCHICAL DEPTH BUFFER BACK ANNOTATON

LOW GRANULARITY COARSE DEPTH TEST EFFICIENCY ENHANCEMENT

GRAPHICS WITH EARLY STENCIL TEST

LOW GRANULARITY COARSE DEPTH TEST EFFICIENCY ENHANCEMENT

HIERARCHICAL DEPTH BUFFER BACK ANNOTATON