Vani Verma

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Two-sided die in a four-sided leadframe based package
- Patent number 8,395,246
- Issue date Mar 12, 2013
- SanDisk Technologies Inc.
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a two-sided die in a four-sided leadframe bas...
- Patent number 8,349,655
- Issue date Jan 8, 2013
- SanDisk Technologies Inc.
- Cheeman Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a two-sided die in a four-sided leadframe bas...
- Patent number 8,058,099
- Issue date Nov 15, 2011
- SanDisk Technologies Inc.
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory module having interconnected and stacked integrated circuits
- Patent number 7,432,599
- Issue date Oct 7, 2008
- Sandisk 3D LLC
- Vani Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-stick detection method and mechanism for array molded laminate...
- Patent number 7,391,104
- Issue date Jun 24, 2008
- Cypress Semiconductor Corporation
- Bo Chang
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for universal packaging in conjunction with a bac...
- Patent number 7,105,377
- Issue date Sep 12, 2006
- Cypress Semiconductor Corporation
- Bo Soon Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory module having interconnected and stacked integrated circuits
- Patent number 7,005,730
- Issue date Feb 28, 2006
- Matrix Semiconductor, Inc.
- Vani Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-stick detection method and mechanism for array molded laminate...
- Patent number 6,853,202
- Issue date Feb 8, 2005
- Cypress Semiconductor Corporation
- Bo Chang
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for universal packaging in conjunction with a bac...
- Patent number 6,730,532
- Issue date May 4, 2004
- Cypress Semiconductor Corporation
- Bo Soon Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory module having interconnected and stacked integrated circuits
- Patent number 6,731,011
- Issue date May 4, 2004
- Matrix Semiconductor, Inc.
- Vani Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for producing high reliability lead frame and packaging sem...
- Patent number 6,576,491
- Issue date Jun 10, 2003
- Cypress Semiconductor Corporation
- Bo Soon Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for delamination-resistant, array type molding...
- Patent number 6,562,272
- Issue date May 13, 2003
- Cypress Semiconductor Corporation
- Bo Chang
- B29 - WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
Information Patent Grant
High reliability lead frame and packaging technology containing the...
- Patent number 6,331,728
- Issue date Dec 18, 2001
- Cypress Semiconductor Corporation
- Bo Soon Chang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE
- Publication number 20130200507
- Publication date Aug 8, 2013
- SANDISK TECHNOLOGIES INC.
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BAS...
- Publication number 20100255640
- Publication date Oct 7, 2010
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE
- Publication number 20090001534
- Publication date Jan 1, 2009
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BAS...
- Publication number 20090004782
- Publication date Jan 1, 2009
- Cheemen Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory module having interconnected and stacked integrated circuits
- Publication number 20060118927
- Publication date Jun 8, 2006
- MATRIX SEMICONDUCTOR, INC.
- Vani Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory module having interconnected and stacked integrated circuits
- Publication number 20040169285
- Publication date Sep 2, 2004
- Vani Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory module having interconnected and stacked integrated circuits
- Publication number 20030155659
- Publication date Aug 21, 2003
- Vani Verma
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Two-sided die in a four-sided leadframe based package

Method of fabricating a two-sided die in a four-sided leadframe bas...

Method of fabricating a two-sided die in a four-sided leadframe bas...

Memory module having interconnected and stacked integrated circuits

Non-stick detection method and mechanism for array molded laminate...

Method and system for universal packaging in conjunction with a bac...

Memory module having interconnected and stacked integrated circuits

Non-stick detection method and mechanism for array molded laminate...

Method and system for universal packaging in conjunction with a bac...

Memory module having interconnected and stacked integrated circuits

Methods for producing high reliability lead frame and packaging sem...

Apparatus and method for delamination-resistant, array type molding...

High reliability lead frame and packaging technology containing the...

Patents Applicationslast 30 patents

TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE

METHOD OF FABRICATING A TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BAS...

TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE

METHOD OF FABRICATING A TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BAS...

Memory module having interconnected and stacked integrated circuits

Memory module having interconnected and stacked integrated circuits

Memory module having interconnected and stacked integrated circuits