VARGHESE GEORGE

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,182,035
- Issue date Dec 31, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic array of arbitrary physical and logical depth
- Patent number 12,174,783
- Issue date Dec 24, 2024
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling product SKUs based on chiplet configurations
- Patent number 12,141,890
- Issue date Nov 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,124,383
- Issue date Oct 22, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalar core integration
- Patent number 12,117,962
- Issue date Oct 15, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 12,112,398
- Issue date Oct 8, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression techniques
- Patent number 12,093,210
- Issue date Sep 17, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor operation scheduling for deterministic latency
- Patent number 12,079,155
- Issue date Sep 3, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,066,975
- Issue date Aug 20, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 12,056,789
- Issue date Aug 6, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,056,059
- Issue date Aug 6, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable sparse matrix multiply acceleration using systolic arrays...
- Patent number 12,039,001
- Issue date Jul 16, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient data sharing for graphics data processing operations
- Patent number 12,032,496
- Issue date Jul 9, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile architecture for graphics operations
- Patent number 12,013,808
- Issue date Jun 18, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processors and graphics processing units having dot produc...
- Patent number 12,007,935
- Issue date Jun 11, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management for detecting cross tile access provid...
- Patent number 11,995,029
- Issue date May 28, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Utilizing structured sparsity in systolic arrays
- Patent number 11,977,885
- Issue date May 7, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processors and graphics processing units having dot produc...
- Patent number 11,954,063
- Issue date Apr 9, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic memory reconfiguration
- Patent number 11,954,062
- Issue date Apr 9, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assistance for hardware prefetch in cache access
- Patent number 11,934,342
- Issue date Mar 19, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods to skip inconsequential matrix operations
- Patent number 11,900,114
- Issue date Feb 13, 2024
- Intel Corporation
- Elmoustapha Ould-Ahmed-Vall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction based control of memory attributes
- Patent number 11,899,614
- Issue date Feb 13, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for exploiting queues and transitional storage...
- Patent number 11,869,113
- Issue date Jan 9, 2024
- Intel Corporation
- Aravindh Anantaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory prefetching in multiple GPU environment
- Patent number 11,861,759
- Issue date Jan 2, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dot product operations on sparse matrix elements
- Patent number 11,842,423
- Issue date Dec 12, 2023
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for synchronization of multi-thread lanes
- Patent number 11,816,500
- Issue date Nov 14, 2023
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250004981
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...
- Publication number 20240427847
- Publication date Dec 26, 2024
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT DATA SHARING FOR GRAPHICS DATA PROCESSING OPERATIONS
- Publication number 20240385975
- Publication date Nov 21, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS
- Publication number 20240320000
- Publication date Sep 26, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20240256483
- Publication date Aug 1, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...
- Publication number 20240256274
- Publication date Aug 1, 2024
- Intel Corporation
- Naveen Mellempudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC MEMORY RECONFIGURATION
- Publication number 20240184739
- Publication date Jun 6, 2024
- Intel Corporation
- Joydeep RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR EXPLOITING QUEUES AND TRANSITIONAL STORAGE...
- Publication number 20240169466
- Publication date May 23, 2024
- Intel Corporation
- Aravindh Anantaraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT
- Publication number 20240161226
- Publication date May 16, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
- Publication number 20240161227
- Publication date May 16, 2024
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES
- Publication number 20240103910
- Publication date Mar 28, 2024
- Intel Corporation
- Valentin Andrei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...
- Publication number 20240086357
- Publication date Mar 14, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES
- Publication number 20240086356
- Publication date Mar 14, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUALIZATION AND MULTI-TENANCY SUPPORT IN GRAPHICS PROCESSORS
- Publication number 20240061700
- Publication date Feb 22, 2024
- Intel Corporation
- Rajesh SANKARAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES
- Publication number 20240053985
- Publication date Feb 15, 2024
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALAR CORE INTEGRATION
- Publication number 20240045830
- Publication date Feb 8, 2024
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT DATA SHARING FOR GRAPHICS DATA PROCESSING OPERATIONS
- Publication number 20240012767
- Publication date Jan 11, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20240013338
- Publication date Jan 11, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20240005443
- Publication date Jan 4, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS ARCHITECTURE INCLUDING A NEURAL NETWORK PIPELINE
- Publication number 20230360307
- Publication date Nov 9, 2023
- Intel Corporation
- HUGUES LABBE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20230351543
- Publication date Nov 2, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE
- Publication number 20230297373
- Publication date Sep 21, 2023
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...
- Publication number 20230281272
- Publication date Sep 7, 2023
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20230195685
- Publication date Jun 22, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR MEMORY ACCESS ARCHITECTURE WITH ADDRESS SORTING
- Publication number 20230104845
- Publication date Apr 6, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING

VARGHESE GEORGE

Person

Patents Grantslast 30 patents

Multi-tile memory management

Systems and methods for cache optimization

Systolic array of arbitrary physical and logical depth

Cache structure and utilization

Systolic disaggregation within a matrix accelerator architecture

Enabling product SKUs based on chiplet configurations

Systems and methods for cache optimization

Scalar core integration

Disaggregation of system-on-chip (SOC) architecture

Multi-tile memory management

Compression techniques

Graphics processor operation scheduling for deterministic latency

Cache structure and utilization

Disaggregation of system-on-chip (SOC) architecture

Systems and methods for cache optimization

Scalable sparse matrix multiply acceleration using systolic arrays...

Efficient data sharing for graphics data processing operations

Multi-tile architecture for graphics operations

Graphics processors and graphics processing units having dot produc...

Multi-tile memory management for detecting cross tile access provid...

Utilizing structured sparsity in systolic arrays

Graphics processors and graphics processing units having dot produc...

Dynamic memory reconfiguration

Assistance for hardware prefetch in cache access

Systems and methods to skip inconsequential matrix operations

Instruction based control of memory attributes

Systems and methods for exploiting queues and transitional storage...

Memory prefetching in multiple GPU environment

Dot product operations on sparse matrix elements

Systems and methods for synchronization of multi-thread lanes

Patents Applicationslast 30 patents

MULTI-TILE MEMORY MANAGEMENT

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...

CACHE STRUCTURE AND UTILIZATION

COMPRESSION TECHNIQUES

EFFICIENT DATA SHARING FOR GRAPHICS DATA PROCESSING OPERATIONS

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCH...

DYNAMIC MEMORY RECONFIGURATION

SYSTEMS AND METHODS FOR EXPLOITING QUEUES AND TRANSITIONAL STORAGE...

MEMORY PREFETCHING IN MULTIPLE GPU ENVIRONMENT

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

SYSTEMS AND METHODS FOR SYNCHRONIZATION OF MULTI-THREAD LANES

SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...

INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES

VIRTUALIZATION AND MULTI-TENANCY SUPPORT IN GRAPHICS PROCESSORS

SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES

SCALAR CORE INTEGRATION

EFFICIENT DATA SHARING FOR GRAPHICS DATA PROCESSING OPERATIONS

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

GRAPHICS ARCHITECTURE INCLUDING A NEURAL NETWORK PIPELINE

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE

INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

GRAPHICS PROCESSOR MEMORY ACCESS ARCHITECTURE WITH ADDRESS SORTING