Vedaraman Geetha

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
High performance interconnect
- Patent number 12,197,357
- Issue date Jan 14, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 12,189,550
- Issue date Jan 7, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for memory bandwidth control
- Patent number 11,899,964
- Issue date Feb 13, 2024
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,899,615
- Issue date Feb 13, 2024
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for memory bandwidth control
- Patent number 11,829,637
- Issue date Nov 28, 2023
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for performing data movement operations with read...
- Patent number 11,816,036
- Issue date Nov 14, 2023
- Intel Corporation
- Anil Vasudevan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for memory bandwidth control
- Patent number 11,789,645
- Issue date Oct 17, 2023
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 11,741,030
- Issue date Aug 29, 2023
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid directory and snoopy-based coherency to reduce directory upd...
- Patent number 11,669,454
- Issue date Jun 6, 2023
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,586,579
- Issue date Feb 21, 2023
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for performing data movement operations with read...
- Patent number 11,327,894
- Issue date May 10, 2022
- Intel Corporation
- Anil Vasudevan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 11,294,852
- Issue date Apr 5, 2022
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 11,269,793
- Issue date Mar 8, 2022
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple dies hardware processors and methods
- Patent number 10,795,853
- Issue date Oct 6, 2020
- Intel Corporation
- Nevine Nassif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock signal modulation for processors
- Patent number 10,782,729
- Issue date Sep 22, 2020
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for performing data movement operations with read...
- Patent number 10,606,755
- Issue date Mar 31, 2020
- Intel Corporation
- Anil Vasudevan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mission-critical computing architecture
- Patent number 10,514,990
- Issue date Dec 24, 2019
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective memory mode authorization enforcement
- Patent number 10,379,768
- Issue date Aug 13, 2019
- Intel Corporation
- Mahesh S. Natu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 10,248,591
- Issue date Apr 2, 2019
- Intel Corporation
- Robert J. Safranek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Value of forward state by increasing local caching agent forwarding
- Patent number 10,204,049
- Issue date Feb 12, 2019
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two level memory full line writes
- Patent number 10,140,213
- Issue date Nov 27, 2018
- Intel Corporation
- Robert G. Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a non-power-of-2 size cache in a first lev...
- Patent number 10,042,562
- Issue date Aug 7, 2018
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementation of reserved cache slots in computing system having i...
- Patent number 10,007,606
- Issue date Jun 26, 2018
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a non-power-of-2 size cache in a first lev...
- Patent number 9,747,041
- Issue date Aug 29, 2017
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 9,626,321
- Issue date Apr 18, 2017
- Intel Corporation
- Robert J. Safranek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Two level memory full line writes
- Patent number 9,619,396
- Issue date Apr 11, 2017
- Intel Corporation
- Robert G. Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for optimizing cache memory transactio...
- Patent number 9,606,925
- Issue date Mar 28, 2017
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherency apparatus and method minimizing memory writeback op...
- Patent number 9,436,605
- Issue date Sep 6, 2016
- Intel Corporation
- Jeffrey D. Chamberlain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inclusive and non-inclusive tracking of local cache lines to avoid...
- Patent number 9,418,009
- Issue date Aug 16, 2016
- Intel Corporation
- Adrian C. Moga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for handling cache misses in a processor
- Patent number 9,405,687
- Issue date Aug 2, 2016
- Intel Corporation
- Bahaa Fahim
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Patents Applicationslast 30 patents

Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20240012772
- Publication date Jan 11, 2024
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR MEMORY BANDWIDTH CONTROL
- Publication number 20230195364
- Publication date Jun 22, 2023
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR MEMORY BANDWIDTH CONTROL
- Publication number 20230195365
- Publication date Jun 22, 2023
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20230169032
- Publication date Jun 1, 2023
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Systems for Memory Bandwidth Control
- Publication number 20230067749
- Publication date Mar 2, 2023
- NUVIA, INC.
- Ramkumar SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR PERFORMING DATA MOVEMENT OPERATIONS WITH READ...
- Publication number 20220261351
- Publication date Aug 18, 2022
- Intel Corporation
- Anil Vasudevan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20220114122
- Publication date Apr 14, 2022
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20220050805
- Publication date Feb 17, 2022
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20210117350
- Publication date Apr 22, 2021
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR PERFORMING DATA MOVEMENT OPERATIONS WITH READ...
- Publication number 20210049102
- Publication date Feb 18, 2021
- Intel Corporation
- Anil Vasudevan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20200356502
- Publication date Nov 12, 2020
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID DIRECTORY AND SNOOPY-BASED COHERENCY TO REDUCE DIRECTORY UPD...
- Publication number 20200356482
- Publication date Nov 12, 2020
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20200334196
- Publication date Oct 22, 2020
- Intel Corporation
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20190391939
- Publication date Dec 26, 2019
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MISSION-CRITICAL COMPUTING ARCHITECTURE
- Publication number 20190163583
- Publication date May 30, 2019
- Intel Corporation
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Signal Modulation for Processors
- Publication number 20190163229
- Publication date May 30, 2019
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR PERFORMING DATA MOVEMENT OPERATIONS WITH READ...
- Publication number 20190004958
- Publication date Jan 3, 2019
- Intel Corporation
- Anil Vasudevan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE DIES HARDWARE PROCESSORS AND METHODS
- Publication number 20180101502
- Publication date Apr 12, 2018
- NEVINE NASSIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE MEMORY MODE AUTHORIZATION ENFORCEMENT
- Publication number 20180095692
- Publication date Apr 5, 2018
- Intel Corporation
- Mahesh S. NATU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALUE OF FORWARD STATE BY INCREASING LOCAL CACHING AGENT FORWARDING
- Publication number 20180081808
- Publication date Mar 22, 2018
- Intel Corporation
- Vedaraman GEETHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...
- Publication number 20180004433
- Publication date Jan 4, 2018
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO LEVEL MEMORY FULL LINE WRITES
- Publication number 20170337134
- Publication date Nov 23, 2017
- Intel Corporation
- Robert G. Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementation of Reserved Cache Slots in Computing System Having I...
- Publication number 20170286298
- Publication date Oct 5, 2017
- Intel Corporation
- Vedaraman GEETHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cpu remote snoop filtering mechanism for field programmable gate array
- Publication number 20170185515
- Publication date Jun 29, 2017
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...
- Publication number 20170185315
- Publication date Jun 29, 2017
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL
- Publication number 20170109286
- Publication date Apr 20, 2017
- Intel Corporation
- Robert G. Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20170109315
- Publication date Apr 20, 2017
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR OPTIMIZING CACHE MEMORY TRANSACTI...
- Publication number 20160283382
- Publication date Sep 29, 2016
- Bahaa Fahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO LEVEL MEMORY FULL LINE WRITES
- Publication number 20160283388
- Publication date Sep 29, 2016
- Intel Corporation
- Robert G. Blankenship
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near...
- Publication number 20150186275
- Publication date Jul 2, 2015
- Adrian C. Moga
- G06 - COMPUTING CALCULATING COUNTING

Vedaraman Geetha

Person

Patents Grantslast 30 patents

High performance interconnect

High performance interconnect

Methods and systems for memory bandwidth control

Multiple dies hardware processors and methods

Methods and systems for memory bandwidth control

Method and system for performing data movement operations with read...

Methods and systems for memory bandwidth control

High performance interconnect

Hybrid directory and snoopy-based coherency to reduce directory upd...

Multiple dies hardware processors and methods

Method and system for performing data movement operations with read...

Multiple dies hardware processors and methods

High performance interconnect

Multiple dies hardware processors and methods

Clock signal modulation for processors

Method and system for performing data movement operations with read...

Mission-critical computing architecture

Selective memory mode authorization enforcement

High performance interconnect

Value of forward state by increasing local caching agent forwarding

Two level memory full line writes

Apparatus and method for a non-power-of-2 size cache in a first lev...

Implementation of reserved cache slots in computing system having i...

Apparatus and method for a non-power-of-2 size cache in a first lev...

High performance interconnect

Two level memory full line writes

Method, apparatus and system for optimizing cache memory transactio...

Cache coherency apparatus and method minimizing memory writeback op...

Inclusive and non-inclusive tracking of local cache lines to avoid...

Method, apparatus and system for handling cache misses in a processor

Patents Applicationslast 30 patents

HIGH PERFORMANCE INTERCONNECT

METHODS AND SYSTEMS FOR MEMORY BANDWIDTH CONTROL

METHODS AND SYSTEMS FOR MEMORY BANDWIDTH CONTROL

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

Methods and Systems for Memory Bandwidth Control

METHOD AND SYSTEM FOR PERFORMING DATA MOVEMENT OPERATIONS WITH READ...

HIGH PERFORMANCE INTERCONNECT

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

HIGH PERFORMANCE INTERCONNECT

METHOD AND SYSTEM FOR PERFORMING DATA MOVEMENT OPERATIONS WITH READ...

HIGH PERFORMANCE INTERCONNECT

HYBRID DIRECTORY AND SNOOPY-BASED COHERENCY TO REDUCE DIRECTORY UPD...

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

HIGH PERFORMANCE INTERCONNECT

MISSION-CRITICAL COMPUTING ARCHITECTURE

Clock Signal Modulation for Processors

METHOD AND SYSTEM FOR PERFORMING DATA MOVEMENT OPERATIONS WITH READ...

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

SELECTIVE MEMORY MODE AUTHORIZATION ENFORCEMENT

VALUE OF FORWARD STATE BY INCREASING LOCAL CACHING AGENT FORWARDING

APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...

TWO LEVEL MEMORY FULL LINE WRITES

Implementation of Reserved Cache Slots in Computing System Having I...

Cpu remote snoop filtering mechanism for field programmable gate array

APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...

HIGH PERFORMANCE INTERCONNECT COHERENCE PROTOCOL

HIGH PERFORMANCE INTERCONNECT

METHOD, APPARATUS AND SYSTEM FOR OPTIMIZING CACHE MEMORY TRANSACTI...

TWO LEVEL MEMORY FULL LINE WRITES

Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near...