Veerapaneni Nagbhushan

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Saratoga, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for integrated circuit datapath layout using a...
- Patent number 7,376,922
- Issue date May 20, 2008
- Intel Corporation
- John A. Rushing
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for layout synthesis of regular structures usi...
- Patent number 7,350,174
- Issue date Mar 25, 2008
- Intel Corporation
- Vinoo N. Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for layout synthesis of regular structures usi...
- Patent number 6,757,878
- Issue date Jun 29, 2004
- Intel Corporation
- Vinoo N. Srinivasan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and apparatus for integrated circuit datapath layout using a...
- Publication number 20050071795
- Publication date Mar 31, 2005
- John A. Rushing
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for layout synthesis of regular structures usi...
- Publication number 20040243963
- Publication date Dec 2, 2004
- Vinoo N. Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for layout synthesis of regular structures usi...
- Publication number 20030126571
- Publication date Jul 3, 2003
- Vinoo N. Srinivasan
- G06 - COMPUTING CALCULATING COUNTING