Venkata DEVARASETTY

Person

Hyderabad, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Smart resource allocation framework for dynamic allocation of syste...
- Patent number 12,032,426
- Issue date Jul 9, 2024
- QUALCOMM Incorporated
- Karthik Rangaraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance aware partial cache collapse
- Patent number 11,940,914
- Issue date Mar 26, 2024
- QUALCOMM Incorporated
- Hithesh Hassan Lepaksha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Access optimized partial cache collapse
- Patent number 11,836,086
- Issue date Dec 5, 2023
- QUALCOMM Incorporated
- Hithesh Hassan Lepaksha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic voltage selection for a single power rail in a multi-core d...
- Patent number 11,221,667
- Issue date Jan 11, 2022
- QUALCOMM Incorporated
- Venkatesh Ravipati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quick energy efficient reboot from ultra-low power mode for a syste...
- Patent number 10,474,224
- Issue date Nov 12, 2019
- QUALCOMM Incorporated
- Deva Sudhir Kumar Pulivendula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Advanced fall through mechanism for low power sequencers
- Patent number 10,338,655
- Issue date Jul 2, 2019
- QUALCOMM Incorporated
- Sarbartha Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-aware CPU power grid design
- Patent number 9,658,671
- Issue date May 23, 2017
- QUALCOMM Incorporated
- Harshit Tiwari
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SMART RESOURCE ALLOCATION FRAMEWORK FOR DYNAMIC ALLOCATION OF SYSTE...
- Publication number 20240061490
- Publication date Feb 22, 2024
- QUALCOMM Incorporated
- Karthik RANGARAJU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMANCE AWARE PARTIAL CACHE COLLAPSE
- Publication number 20230401152
- Publication date Dec 14, 2023
- QUALCOMM Incorporated
- Hithesh Hassan LEPAKSHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESS OPTIMIZED PARTIAL CACHE COLLAPSE
- Publication number 20230401156
- Publication date Dec 14, 2023
- QUALCOMM Incorporated
- Hithesh Hassan LEPAKSHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC VOLTAGE SELECTION FOR A SINGLE POWER RAIL IN A MULTI-CORE D...
- Publication number 20220035437
- Publication date Feb 3, 2022
- QUALCOMM Incorporated
- Venkatesh RAVIPATI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLIENT LATENCY-AWARE MICRO-IDLE MEMORY POWER MANAGEMENT
- Publication number 20200058330
- Publication date Feb 20, 2020
- QUALCOMM Incorporated
- PAWAN CHHABRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADVANCED FALL THROUGH MECHANISM FOR LOW POWER SEQUENCERS
- Publication number 20180292875
- Publication date Oct 11, 2018
- QUALCOMM Incorporated
- Sarbartha Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUICK ENERGY EFFICIENT REBOOT FROM ULTRA-LOW POWER MODE FOR A SYSTE...
- Publication number 20180267598
- Publication date Sep 20, 2018
- QUALCOMM Incorporated
- Deva Sudhir Kumar Pulivendula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER-AWARE CPU POWER GRID DESIGN
- Publication number 20170090539
- Publication date Mar 30, 2017
- QUALCOMM Incorporated
- Harshit TIWARI
- G06 - COMPUTING CALCULATING COUNTING

Venkata DEVARASETTY

Person

Patents Grantslast 30 patents

Smart resource allocation framework for dynamic allocation of syste...

Performance aware partial cache collapse

Access optimized partial cache collapse

Dynamic voltage selection for a single power rail in a multi-core d...

Quick energy efficient reboot from ultra-low power mode for a syste...

Advanced fall through mechanism for low power sequencers

Power-aware CPU power grid design

Patents Applicationslast 30 patents

SMART RESOURCE ALLOCATION FRAMEWORK FOR DYNAMIC ALLOCATION OF SYSTE...

PERFORMANCE AWARE PARTIAL CACHE COLLAPSE

ACCESS OPTIMIZED PARTIAL CACHE COLLAPSE

DYNAMIC VOLTAGE SELECTION FOR A SINGLE POWER RAIL IN A MULTI-CORE D...

CLIENT LATENCY-AWARE MICRO-IDLE MEMORY POWER MANAGEMENT

ADVANCED FALL THROUGH MECHANISM FOR LOW POWER SEQUENCERS

QUICK ENERGY EFFICIENT REBOOT FROM ULTRA-LOW POWER MODE FOR A SYSTE...

POWER-AWARE CPU POWER GRID DESIGN