Venkata Narayanan Srinivasan

Person

Greater Noida, IN

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for parallel testing of electronic device
- Patent number 12,203,982
- Issue date Jan 21, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Rajesh Narwal
- G01 - MEASURING TESTING
Information Patent Grant
TVF transition coverage with self-test and production-test time red...
- Patent number 12,146,911
- Issue date Nov 19, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
ATPG testing method for latch based memories, for area reduction
- Patent number 12,020,760
- Issue date Jun 25, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Reset and safe state logic generation in dual power flow devices
- Patent number 11,983,025
- Issue date May 14, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-test controller, and associated method
- Patent number 11,835,991
- Issue date Dec 5, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Amulya Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan circuit and method
- Patent number 11,726,140
- Issue date Aug 15, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for scan testing
- Patent number 11,714,131
- Issue date Aug 1, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Automatic test pattern generation circuitry in multi power domain s...
- Patent number 11,680,982
- Issue date Jun 20, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ATPG testing method for latch based memories, for area reduction
- Patent number 11,557,364
- Issue date Jan 17, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and devices for bypassing a voltage regulator
- Patent number 11,550,348
- Issue date Jan 10, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Reset and safe state logic generation in dual power flow devices
- Patent number 11,513,544
- Issue date Nov 29, 2022
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Isolation logic test circuit and associated test method
- Patent number 11,442,108
- Issue date Sep 13, 2022
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
System and method for parallel testing of electronic device
- Patent number 11,340,292
- Issue date May 24, 2022
- STMicroelectronics International N.V.
- Rajesh Narwal
- G01 - MEASURING TESTING
Information Patent Grant
Isolation enable test coverage for multiple power domains
- Patent number 11,119,153
- Issue date Sep 14, 2021
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Combinatorial serial and parallel test access port selection in a J...
- Patent number 11,041,905
- Issue date Jun 22, 2021
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for testing voltage monitors
- Patent number 10,996,266
- Issue date May 4, 2021
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Sequential test access port selection in a JTAG interface
- Patent number 10,890,619
- Issue date Jan 12, 2021
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit for dynamic checking for faults on functional and BIST...
- Patent number 10,802,077
- Issue date Oct 13, 2020
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Test circuit for electronic device permitting interface control bet...
- Patent number 10,747,282
- Issue date Aug 18, 2020
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry for testing non-maskable voltage monitor for power manage...
- Patent number 10,620,267
- Issue date Apr 14, 2020
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Voltage regulator bypass circuitry usable during device testing ope...
- Patent number 10,527,672
- Issue date Jan 7, 2020
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Voltage level monitoring of an integrated circuit for production te...
- Patent number 10,502,784
- Issue date Dec 10, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Combinatorial serial and parallel test access port selection in a J...
- Patent number 10,495,690
- Issue date Dec 3, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock selection circuit and test clock generation circuit for LBIST...
- Patent number 10,393,804
- Issue date Aug 27, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Sequential test access port selection in a JTAG interface
- Patent number 10,386,411
- Issue date Aug 20, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Clock selection circuit and test clock generation circuit for LBIST...
- Patent number 10,228,420
- Issue date Mar 12, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic built-in self-test (LBIST) with pipeline scan enable launch o...
- Patent number 10,151,797
- Issue date Dec 11, 2018
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Stuck-at fault detection on the clock tree buffers of a clock source
- Patent number 10,048,315
- Issue date Aug 14, 2018
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Testing of power on reset (POR) and unmaskable voltage monitors
- Patent number 9,941,875
- Issue date Apr 10, 2018
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Testing of power on reset (POR) and unmaskable voltage monitors
- Patent number 9,698,771
- Issue date Jul 4, 2017
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...
- Publication number 20240402249
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION
- Publication number 20240296899
- Publication date Sep 5, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G11 - INFORMATION STORAGE
Information Patent Application
PORs TESTING IN MULTIPLE POWER DOMAIN DEVICES
- Publication number 20240264229
- Publication date Aug 8, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
AREA, COST, AND TIME-EFFECTIVE SCAN COVERAGE IMPROVEMENT
- Publication number 20240250668
- Publication date Jul 25, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCAN CIRCUIT AND METHOD
- Publication number 20240012051
- Publication date Jan 11, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESET AND SAFE STATE LOGIC GENERATION IN DUAL POWER FLOW DEVICES
- Publication number 20230168699
- Publication date Jun 1, 2023
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
AUTOMATIC TEST PATTERN GENERATION CIRCUITRY IN MULTI POWER DOMAIN S...
- Publication number 20230128466
- Publication date Apr 27, 2023
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION
- Publication number 20230105305
- Publication date Apr 6, 2023
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G11 - INFORMATION STORAGE
Information Patent Application
ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION
- Publication number 20230042541
- Publication date Feb 9, 2023
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND DEVICES FOR BYPASSING A VOLTAGE REGULATOR
- Publication number 20220308610
- Publication date Sep 29, 2022
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G05 - CONTROLLING REGULATING
Information Patent Application
SELF-TEST CONTROLLER, AND ASSOCIATED METHOD
- Publication number 20220300389
- Publication date Sep 22, 2022
- STMicroelectronics International N.V.
- Amulya Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PARALLEL TESTING OF ELECTRONIC DEVICE
- Publication number 20220276302
- Publication date Sep 1, 2022
- STMicroelectronics International N.V.
- Rajesh Narwal
- G01 - MEASURING TESTING
Information Patent Application
SCAN CIRCUIT AND METHOD
- Publication number 20220244308
- Publication date Aug 4, 2022
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Testing Voltage Monitors
- Publication number 20210041496
- Publication date Feb 11, 2021
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
System and Method for Parallel Testing of Electronic Device
- Publication number 20210011080
- Publication date Jan 14, 2021
- STMicroelectronics International N.V.
- Rajesh Narwal
- G01 - MEASURING TESTING
Information Patent Application
TEST CIRCUIT FOR DYNAMIC CHECKING FOR FAULTS ON FUNCTIONAL AND BIST...
- Publication number 20200333399
- Publication date Oct 22, 2020
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G01 - MEASURING TESTING
Information Patent Application
TEST CIRCUIT FOR ELECTRONIC DEVICE PERMITTING INTERFACE CONTROL BET...
- Publication number 20200125149
- Publication date Apr 23, 2020
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A J...
- Publication number 20200064405
- Publication date Feb 27, 2020
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENTIAL TEST ACCESS PORT SELECTION IN A JTAG INTERFACE
- Publication number 20190331733
- Publication date Oct 31, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
VOLTAGE LEVEL MONITORING OF AN INTEGRATED CIRCUIT FOR PRODUCTION TE...
- Publication number 20190094301
- Publication date Mar 28, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
VOLTAGE REGULATOR BYPASS CIRCUITRY USABLE DURING DEVICE TESTING OPE...
- Publication number 20190094296
- Publication date Mar 28, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUITRY FOR TESTING NON-MASKABLE VOLTAGE MONITOR FOR POWER MANAGE...
- Publication number 20190086474
- Publication date Mar 21, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK SELECTION CIRCUIT AND TEST CLOCK GENERATION CIRCUIT FOR LBIST...
- Publication number 20190064268
- Publication date Feb 28, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A J...
- Publication number 20190064270
- Publication date Feb 28, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENTIAL TEST ACCESS PORT SELECTION IN A JTAG INTERFACE
- Publication number 20190064271
- Publication date Feb 28, 2019
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
CLOCK SELECTION CIRCUIT AND TEST CLOCK GENERATION CIRCUIT FOR LBIST...
- Publication number 20180080987
- Publication date Mar 22, 2018
- STMicroelectronics International N.V
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
LOGIC BUILT-IN SELF-TEST (LBIST) WITH PIPELINE SCAN ENABLE LAUNCH O...
- Publication number 20180031631
- Publication date Feb 1, 2018
- STMicroelectronics International N.V
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
TESTING OF POWER ON RESET (POR) AND UNMASKABLE VOLTAGE MONITORS
- Publication number 20180013418
- Publication date Jan 11, 2018
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STUCK-AT FAULT DETECTION ON THE CLOCK TREE BUFFERS OF A CLOCK SOURCE
- Publication number 20180011141
- Publication date Jan 11, 2018
- STMicroelectronics International N.V
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING

Venkata Narayanan Srinivasan

Person

Patents Grantslast 30 patents

System and method for parallel testing of electronic device

TVF transition coverage with self-test and production-test time red...

ATPG testing method for latch based memories, for area reduction

Reset and safe state logic generation in dual power flow devices

Self-test controller, and associated method

Scan circuit and method

Circuit and method for scan testing

Automatic test pattern generation circuitry in multi power domain s...

ATPG testing method for latch based memories, for area reduction

Methods and devices for bypassing a voltage regulator

Reset and safe state logic generation in dual power flow devices

Isolation logic test circuit and associated test method

System and method for parallel testing of electronic device

Isolation enable test coverage for multiple power domains

Combinatorial serial and parallel test access port selection in a J...

System and method for testing voltage monitors

Sequential test access port selection in a JTAG interface

Test circuit for dynamic checking for faults on functional and BIST...

Test circuit for electronic device permitting interface control bet...

Circuitry for testing non-maskable voltage monitor for power manage...

Voltage regulator bypass circuitry usable during device testing ope...

Voltage level monitoring of an integrated circuit for production te...

Combinatorial serial and parallel test access port selection in a J...

Clock selection circuit and test clock generation circuit for LBIST...

Sequential test access port selection in a JTAG interface

Clock selection circuit and test clock generation circuit for LBIST...

Logic built-in self-test (LBIST) with pipeline scan enable launch o...

Stuck-at fault detection on the clock tree buffers of a clock source

Testing of power on reset (POR) and unmaskable voltage monitors

Testing of power on reset (POR) and unmaskable voltage monitors

Patents Applicationslast 30 patents

TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...

ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION

PORs TESTING IN MULTIPLE POWER DOMAIN DEVICES

AREA, COST, AND TIME-EFFECTIVE SCAN COVERAGE IMPROVEMENT

SCAN CIRCUIT AND METHOD

RESET AND SAFE STATE LOGIC GENERATION IN DUAL POWER FLOW DEVICES

AUTOMATIC TEST PATTERN GENERATION CIRCUITRY IN MULTI POWER DOMAIN S...

ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION

ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION

METHODS AND DEVICES FOR BYPASSING A VOLTAGE REGULATOR

SELF-TEST CONTROLLER, AND ASSOCIATED METHOD

SYSTEM AND METHOD FOR PARALLEL TESTING OF ELECTRONIC DEVICE

SCAN CIRCUIT AND METHOD

System and Method for Testing Voltage Monitors

System and Method for Parallel Testing of Electronic Device

TEST CIRCUIT FOR DYNAMIC CHECKING FOR FAULTS ON FUNCTIONAL AND BIST...

TEST CIRCUIT FOR ELECTRONIC DEVICE PERMITTING INTERFACE CONTROL BET...

COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A J...

SEQUENTIAL TEST ACCESS PORT SELECTION IN A JTAG INTERFACE

VOLTAGE LEVEL MONITORING OF AN INTEGRATED CIRCUIT FOR PRODUCTION TE...

VOLTAGE REGULATOR BYPASS CIRCUITRY USABLE DURING DEVICE TESTING OPE...

CIRCUITRY FOR TESTING NON-MASKABLE VOLTAGE MONITOR FOR POWER MANAGE...

CLOCK SELECTION CIRCUIT AND TEST CLOCK GENERATION CIRCUIT FOR LBIST...

COMBINATORIAL SERIAL AND PARALLEL TEST ACCESS PORT SELECTION IN A J...

SEQUENTIAL TEST ACCESS PORT SELECTION IN A JTAG INTERFACE

CLOCK SELECTION CIRCUIT AND TEST CLOCK GENERATION CIRCUIT FOR LBIST...

LOGIC BUILT-IN SELF-TEST (LBIST) WITH PIPELINE SCAN ENABLE LAUNCH O...

TESTING OF POWER ON RESET (POR) AND UNMASKABLE VOLTAGE MONITORS

STUCK-AT FAULT DETECTION ON THE CLOCK TREE BUFFERS OF A CLOCK SOURCE