Venkatesh P. Gopinath

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Partitioned memory architecture with single resistor or dual resist...
- Patent number 12,125,530
- Issue date Oct 22, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Grant
Partitioned memory architecture with dual resistor memory elements...
- Patent number 12,106,804
- Issue date Oct 1, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure including a cross-bar router and method
- Patent number 12,027,226
- Issue date Jul 2, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold voltage-programmable field effect transistor-based memory...
- Patent number 11,990,171
- Issue date May 21, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable delay circuit including threshold-voltage programmable...
- Patent number 11,855,642
- Issue date Dec 26, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory device having programmable impedance elements with a common...
- Patent number 11,056,646
- Issue date Jul 6, 2021
- Adesto Technologies Corporation
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reference circuits and methods for resistive memories
- Patent number 10,984,861
- Issue date Apr 20, 2021
- Adesto Technologies Corporation
- Ishai Naveh
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memories with programmable impedance elements...
- Patent number 10,777,268
- Issue date Sep 15, 2020
- Adesto Technologies Corporation
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable impedance memory device and related methods
- Patent number 10,181,496
- Issue date Jan 15, 2019
- Adesto Technologies Corporation
- Ming Sang Kwan
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive switching devices having a switching layer and an interme...
- Patent number 9,818,939
- Issue date Nov 14, 2017
- Adesto Technologies Corporation
- John R. Jameson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resistive switching memory having a resistor, diode, and switch mem...
- Patent number 9,530,495
- Issue date Dec 27, 2016
- Adesto Technologies Corporation
- John Dinh
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual program state cycling algorithms for resistive switching memor...
- Patent number 9,524,777
- Issue date Dec 20, 2016
- Adesto Technologies Corporation
- Deepak Kamalanathan
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive switching memory with cell access by analog signal contro...
- Patent number 9,472,272
- Issue date Oct 18, 2016
- Adesto Technologies Corporation
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cells with vertically integrated tunnel access device and pr...
- Patent number 9,391,270
- Issue date Jul 12, 2016
- Adesto Technologies Corporation
- Venkatesh P. Gopinath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuits and methods for placing programmable impedance memory elem...
- Patent number 9,368,198
- Issue date Jun 14, 2016
- Adesto Technologies Corporation
- Deepak Kamalanathan
- G11 - INFORMATION STORAGE
Information Patent Grant
Capacitor arrangements using a resistive switching memory cell stru...
- Patent number 9,368,206
- Issue date Jun 14, 2016
- Adesto Technologies Corporation
- John Dinh
- G11 - INFORMATION STORAGE
Information Patent Grant
Solid electrolyte based memory devices and methods having adaptable...
- Patent number 9,305,643
- Issue date Apr 5, 2016
- Adesto Technologies Corporation
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-conditioning circuits and methods for programmable impedance el...
- Patent number 9,025,396
- Issue date May 5, 2015
- Adesto Technologies Corporation
- Foroozan Sarah Koushan
- G11 - INFORMATION STORAGE
Information Patent Grant
Safeguarding data through an SMT process
- Patent number 9,007,808
- Issue date Apr 14, 2015
- Adesto Technologies Corporation
- John Dinh
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive switching devices and methods of formation thereof
- Patent number 8,941,089
- Issue date Jan 27, 2015
- Adesto Technologies Corporation
- Chakravarthy Gopalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuits and methods for placing programmable impedance memory elem...
- Patent number 8,730,752
- Issue date May 20, 2014
- Adesto Technologies Corporation
- Deepak Kamalanathan
- G11 - INFORMATION STORAGE
Information Patent Grant
Technique for determining circuit interdependencies
- Patent number 8,099,705
- Issue date Jan 17, 2012
- Oracle America, Inc.
- Paul J. Dickinson
- G01 - MEASURING TESTING
Information Patent Grant
Method characterizing materials for a trench isolation structure ha...
- Patent number 8,021,955
- Issue date Sep 20, 2011
- LSI Logic Corporation
- Venkatesh P. Gopinath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Leakage power optimization considering gate input activity and timi...
- Patent number 7,802,217
- Issue date Sep 21, 2010
- Oracle America, Inc.
- Venkatesh P. Gopinath
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheme for screening weak memory cell
- Patent number 7,679,978
- Issue date Mar 16, 2010
- Sun Microsystems, Inc.
- Hua-Yu Su
- G11 - INFORMATION STORAGE
Information Patent Grant
Shallow trench isolation structure with low trench parasitic capaci...
- Patent number 7,619,294
- Issue date Nov 17, 2009
- LSI Corporation
- Venkatesh P. Gopinath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High k gate insulator removal
- Patent number 7,413,996
- Issue date Aug 19, 2008
- LSI Corporation
- Arvind Kamath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of trenches with multiple depths on the same substrate
- Patent number 7,189,628
- Issue date Mar 13, 2007
- LSI Logic Corporation
- Mohammad R. Mirbedini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an antifuse on a semiconductor substrate using we...
- Patent number 7,026,217
- Issue date Apr 11, 2006
- LSI Logic Corporation
- Arvind Kamath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a shallow trench isolation structure with l...
- Patent number 7,001,823
- Issue date Feb 21, 2006
- LSI Logic Corporation
- Venkatesh P. Gopinath
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
STRUCTURE WITH ISOLATED WELL
- Publication number 20240258320
- Publication date Aug 1, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Siva Kumar CHINTHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-VOLATILE CURRENT MIRROR CIRCUIT WITH PROGRAMMABLE TRANSISTOR
- Publication number 20240241534
- Publication date Jul 18, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- G05 - CONTROLLING REGULATING
Information Patent Application
THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY...
- Publication number 20240221810
- Publication date Jul 4, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE STATIC RANDOM ACCESS MEMORY BIT CELLS WITH FERROELECTR...
- Publication number 20240194253
- Publication date Jun 13, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Pirooz Parvarandeh
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSISTOR ARRAYS WITH CONTROLLABLE GATE VOLTAGE
- Publication number 20240194535
- Publication date Jun 13, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL ARRAY STRUCTURE HAVING BIT LINE FOR REDUCING SIGNAL RES...
- Publication number 20240196629
- Publication date Jun 13, 2024
- GLOBAL FOUNDRIES U.S. Inc.
- Sandeep PURI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BIPOLAR JUNCTION TRANSISTOR ARRAYS
- Publication number 20240170560
- Publication date May 23, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Alexander Derrickson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARRAY ARRANGEMENTS OF VERTICAL BIPOLAR JUNCTION TRANSISTORS
- Publication number 20240172455
- Publication date May 23, 2024
- GLOBALFOUNDRIES U.S. Inc.
- John J. Pekarik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RESISTIVE MEMORY ELEMENTS ACCESSED BY BIPOLAR JUNCTION TRANSISTORS
- Publication number 20240147736
- Publication date May 2, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PARTITIONED MEMORY ARCHITECTURE WITH SINGLE RESISTOR MEMORY ELEMENT...
- Publication number 20240119977
- Publication date Apr 11, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
PARTITIONED MEMORY ARCHITECTURE AND METHOD FOR REPEATEDLY USING THE...
- Publication number 20240119975
- Publication date Apr 11, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
PARTITIONED MEMORY ARCHITECTURE WITH SINGLE RESISTOR OR DUAL RESIST...
- Publication number 20240120001
- Publication date Apr 11, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
CALIBRATION METHODS AND STRUCTURES FOR PARTITIONED MEMORY ARCHITECT...
- Publication number 20240119974
- Publication date Apr 11, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
PARTITIONED MEMORY ARCHITECTURE WITH DUAL RESISTOR MEMORY ELEMENTS...
- Publication number 20240120004
- Publication date Apr 11, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
RESISTIVE MEMORY ELEMENT ARRAYS WITH SHARED ELECTRODE STRIPS
- Publication number 20240023345
- Publication date Jan 18, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
STRUCTURE INCLUDING A CROSS-BAR ROUTER AND METHOD
- Publication number 20240005963
- Publication date Jan 4, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
CAPACITOR INTEGRATED WITH MEMORY ELEMENT OF MEMORY CELL
- Publication number 20230422519
- Publication date Dec 28, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY DEVICE WITH REFERENCE VOLTAGE CIRCUIT
- Publication number 20230402091
- Publication date Dec 14, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY...
- Publication number 20230260561
- Publication date Aug 17, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC RANDOM ACCESS MEMORIES WITH PROGRAMMABLE IMPEDANCE ELEMENTS...
- Publication number 20190348112
- Publication date Nov 14, 2019
- Adesto Technologies Corporation
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE HAVING PROGRAMMABLE IMPEDANCE ELEMENTS WITH A COMMON...
- Publication number 20180205012
- Publication date Jul 19, 2018
- Adesto Technologies Corporation
- Mark T. Ramsbey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RESISTIVE SWITCHING MEMORY WITH CELL ACCESS BY ANALOG SIGNAL CONTRO...
- Publication number 20160247564
- Publication date Aug 25, 2016
- ADESTO TECHNOLOGIES CORPORATION
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive Switching Devices Having a Switching Layer and an Interme...
- Publication number 20160118585
- Publication date Apr 28, 2016
- ADESTO TECHNOLOGIES CORPORATION
- John R. Jameson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROGRAMMABLE IMPEDANCE MEMORY ELEMENTS AND CORRESPONDING METHODS
- Publication number 20140293676
- Publication date Oct 2, 2014
- Wei Ti Lee
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive Switching Devices Having a Switching Layer And An Interme...
- Publication number 20140246641
- Publication date Sep 4, 2014
- ADESTO TECHNOLOGIES CORPORATION
- John R. Jameson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICES AND METHODS HAVING ADAPTABLE READ THRESHOLD LEVELS
- Publication number 20130258753
- Publication date Oct 3, 2013
- ADESTO TECHNOLOGIES CORPORATION
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive Switching Devices and Methods of Formation Thereof
- Publication number 20130214234
- Publication date Aug 22, 2013
- ADESTO TECHNOLOGIES CORPORATION
- Chakravarthy Gopalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUE FOR DETERMINING CIRCUIT INTERDEPENDENCIES
- Publication number 20100281442
- Publication date Nov 4, 2010
- SUN MICROSYSTEMS, INC.
- Paul J. Dickinson
- G01 - MEASURING TESTING
Information Patent Application
Hard mask removal
- Publication number 20050006347
- Publication date Jan 13, 2005
- Venkatesh Gopinath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High k gate insulator removal
- Publication number 20040203246
- Publication date Oct 14, 2004
- Arvind Kamath
- H01 - BASIC ELECTRIC ELEMENTS

Venkatesh P. Gopinath

Person

Patents Grantslast 30 patents

Partitioned memory architecture with single resistor or dual resist...

Partitioned memory architecture with dual resistor memory elements...

Structure including a cross-bar router and method

Threshold voltage-programmable field effect transistor-based memory...

Programmable delay circuit including threshold-voltage programmable...

Memory device having programmable impedance elements with a common...

Reference circuits and methods for resistive memories

Static random access memories with programmable impedance elements...

Programmable impedance memory device and related methods

Resistive switching devices having a switching layer and an interme...

Resistive switching memory having a resistor, diode, and switch mem...

Dual program state cycling algorithms for resistive switching memor...

Resistive switching memory with cell access by analog signal contro...

Memory cells with vertically integrated tunnel access device and pr...

Circuits and methods for placing programmable impedance memory elem...

Capacitor arrangements using a resistive switching memory cell stru...

Solid electrolyte based memory devices and methods having adaptable...

Pre-conditioning circuits and methods for programmable impedance el...

Safeguarding data through an SMT process

Resistive switching devices and methods of formation thereof

Circuits and methods for placing programmable impedance memory elem...

Technique for determining circuit interdependencies

Method characterizing materials for a trench isolation structure ha...

Leakage power optimization considering gate input activity and timi...

Scheme for screening weak memory cell

Shallow trench isolation structure with low trench parasitic capaci...

High k gate insulator removal

Fabrication of trenches with multiple depths on the same substrate

Method of forming an antifuse on a semiconductor substrate using we...

Method of manufacturing a shallow trench isolation structure with l...

Patents Applicationslast 30 patents

STRUCTURE WITH ISOLATED WELL

NON-VOLATILE CURRENT MIRROR CIRCUIT WITH PROGRAMMABLE TRANSISTOR

THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY...

NON-VOLATILE STATIC RANDOM ACCESS MEMORY BIT CELLS WITH FERROELECTR...

TRANSISTOR ARRAYS WITH CONTROLLABLE GATE VOLTAGE

MEMORY CELL ARRAY STRUCTURE HAVING BIT LINE FOR REDUCING SIGNAL RES...

BIPOLAR JUNCTION TRANSISTOR ARRAYS

ARRAY ARRANGEMENTS OF VERTICAL BIPOLAR JUNCTION TRANSISTORS

RESISTIVE MEMORY ELEMENTS ACCESSED BY BIPOLAR JUNCTION TRANSISTORS

PARTITIONED MEMORY ARCHITECTURE WITH SINGLE RESISTOR MEMORY ELEMENT...

PARTITIONED MEMORY ARCHITECTURE AND METHOD FOR REPEATEDLY USING THE...

PARTITIONED MEMORY ARCHITECTURE WITH SINGLE RESISTOR OR DUAL RESIST...

CALIBRATION METHODS AND STRUCTURES FOR PARTITIONED MEMORY ARCHITECT...

PARTITIONED MEMORY ARCHITECTURE WITH DUAL RESISTOR MEMORY ELEMENTS...

RESISTIVE MEMORY ELEMENT ARRAYS WITH SHARED ELECTRODE STRIPS

STRUCTURE INCLUDING A CROSS-BAR ROUTER AND METHOD

CAPACITOR INTEGRATED WITH MEMORY ELEMENT OF MEMORY CELL

NON-VOLATILE MEMORY DEVICE WITH REFERENCE VOLTAGE CIRCUIT

THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY...

STATIC RANDOM ACCESS MEMORIES WITH PROGRAMMABLE IMPEDANCE ELEMENTS...

MEMORY DEVICE HAVING PROGRAMMABLE IMPEDANCE ELEMENTS WITH A COMMON...

RESISTIVE SWITCHING MEMORY WITH CELL ACCESS BY ANALOG SIGNAL CONTRO...

Resistive Switching Devices Having a Switching Layer and an Interme...

PROGRAMMABLE IMPEDANCE MEMORY ELEMENTS AND CORRESPONDING METHODS

Resistive Switching Devices Having a Switching Layer And An Interme...

MEMORY DEVICES AND METHODS HAVING ADAPTABLE READ THRESHOLD LEVELS

Resistive Switching Devices and Methods of Formation Thereof

TECHNIQUE FOR DETERMINING CIRCUIT INTERDEPENDENCIES

Hard mask removal

High k gate insulator removal