Venkatraman Ramakrishnan

Person

Kasturi Nagar, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Boundary port power in pent modelling and management
- Patent number 11,815,971
- Issue date Nov 14, 2023
- Texas Instruments Incorporated
- Lakshmanan Balasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to simulate metastability for circuit design...
- Patent number 11,775,718
- Issue date Oct 3, 2023
- Texas Instruments Incorporated
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation framework
- Patent number 11,574,099
- Issue date Feb 7, 2023
- Texas Instruments Incorporated
- Lakshmanan Balasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to simulate metastability for circuit design...
- Patent number 11,531,798
- Issue date Dec 20, 2022
- Texas Instmments Incorporated
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement aware clock gate cloning and fanout optimization
- Patent number 8,661,374
- Issue date Feb 25, 2014
- Texas Instruments Incorporated
- Ramamurthy Vishweshwara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC design flow incorporating optimal assumptions of power supply vo...
- Patent number 8,051,399
- Issue date Nov 1, 2011
- Texas Instruments Incorporated
- Ramamurthy Vishweshwara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing analysis when integrating multiple circuit blocks while bala...
- Patent number 7,962,872
- Issue date Jun 14, 2011
- Texas Instruments Incorporated
- Arun Koithyar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR AGING AWARE MODELING AND STATIC TIMING ANALYS...
- Publication number 20240330555
- Publication date Oct 3, 2024
- INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR
- Anand Bulusu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING CLOCK TRIGGER SIGNALS FOR ASYNCHRONOUS CLOCK DOMAINS
- Publication number 20240310868
- Publication date Sep 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Gregory North
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CONTROL OF A MULTI-TRIM OSCILLATOR
- Publication number 20240313749
- Publication date Sep 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Gregory North
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND SYSTEM FOR USE WITH AN ELECTRONIC DESIGN AUTOMATION (EDA...
- Publication number 20240256754
- Publication date Aug 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Atul Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
"WEAK" UNDRIVEN STATE MODELLING FOR POWER MANAGEMENT VERIFICATION
- Publication number 20240078369
- Publication date Mar 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lakshmanan BALASUBRAMANIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR COMPREHENSIVE LOW POWER SIMULATION COVERAGE
- Publication number 20230367938
- Publication date Nov 16, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Vivek Gandhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL CDC AND RDC VERIFICATION
- Publication number 20230244841
- Publication date Aug 3, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR MODELING AND VERIFICATION OF CONVERGENCE FOR HIERARC...
- Publication number 20230205969
- Publication date Jun 29, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar SURENDRAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR TIMING SIGNOFF IN MIXED-TRANSISTOR DESIGNS
- Publication number 20230195984
- Publication date Jun 22, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Ajoy MANDAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR DESIGN VERIFICATION OF DOMAIN CROSSINGS
- Publication number 20230110701
- Publication date Apr 13, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar SURENDRAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO SIMULATE METASTABILITY FOR CIRCUIT DESIGN...
- Publication number 20230088503
- Publication date Mar 23, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO SIMULATE METASTABILITY FOR CIRCUIT DESIGN...
- Publication number 20220269845
- Publication date Aug 25, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATION FRAMEWORK
- Publication number 20220083718
- Publication date Mar 17, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lakshmanan Balasubramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDARY PORT POWER INTENT MODELLING AND MANAGEMENT
- Publication number 20210255682
- Publication date Aug 19, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Lakshmanan BALASUBRAMANIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLACEMENT AWARE CLOCK GATE CLONING AND FANOUT OPTIMIZATION
- Publication number 20130174104
- Publication date Jul 4, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Ramamurthy Vishweshwara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Timing Analysis When Integrating Multiple Circuit Blocks While Bala...
- Publication number 20090144674
- Publication date Jun 4, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Arun Koithyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IC Design Flow Incorporating Optimal Assumptions of Power Supply Vo...
- Publication number 20090125858
- Publication date May 14, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Ramamurthy Vishweshwara
- G06 - COMPUTING CALCULATING COUNTING

Venkatraman Ramakrishnan

Person

Patents Grantslast 30 patents

Boundary port power in pent modelling and management

Methods and apparatus to simulate metastability for circuit design...

Simulation framework

Methods and apparatus to simulate metastability for circuit design...

Placement aware clock gate cloning and fanout optimization

IC design flow incorporating optimal assumptions of power supply vo...

Timing analysis when integrating multiple circuit blocks while bala...

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR AGING AWARE MODELING AND STATIC TIMING ANALYS...

MANAGING CLOCK TRIGGER SIGNALS FOR ASYNCHRONOUS CLOCK DOMAINS

DYNAMIC CONTROL OF A MULTI-TRIM OSCILLATOR

METHOD AND SYSTEM FOR USE WITH AN ELECTRONIC DESIGN AUTOMATION (EDA...

"WEAK" UNDRIVEN STATE MODELLING FOR POWER MANAGEMENT VERIFICATION

METHOD FOR COMPREHENSIVE LOW POWER SIMULATION COVERAGE

HIERARCHICAL CDC AND RDC VERIFICATION

TECHNIQUES FOR MODELING AND VERIFICATION OF CONVERGENCE FOR HIERARC...

METHOD FOR TIMING SIGNOFF IN MIXED-TRANSISTOR DESIGNS

TECHNIQUES FOR DESIGN VERIFICATION OF DOMAIN CROSSINGS

METHODS AND APPARATUS TO SIMULATE METASTABILITY FOR CIRCUIT DESIGN...

METHODS AND APPARATUS TO SIMULATE METASTABILITY FOR CIRCUIT DESIGN...

SIMULATION FRAMEWORK

BOUNDARY PORT POWER INTENT MODELLING AND MANAGEMENT

PLACEMENT AWARE CLOCK GATE CLONING AND FANOUT OPTIMIZATION

Timing Analysis When Integrating Multiple Circuit Blocks While Bala...

IC Design Flow Incorporating Optimal Assumptions of Power Supply Vo...