Verma R. Rohit

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sending packets with expanded headers
- Patent number 10,164,880
- Issue date Dec 25, 2018
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for single-ended communication of tran...
- Patent number 9,910,814
- Issue date Mar 6, 2018
- Intel Corporation
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and an apparatus with a sideband interface interconnecting...
- Patent number 9,753,875
- Issue date Sep 5, 2017
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Supporting multiple channels of a single interface
- Patent number 9,489,329
- Issue date Nov 8, 2016
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing error handling support to legacy devices
- Patent number 9,448,870
- Issue date Sep 20, 2016
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggregating completion messages in a sideband interface
- Patent number 9,270,576
- Issue date Feb 23, 2016
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Common idle state, active state and credit management for an interface
- Patent number 9,122,815
- Issue date Sep 1, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Sending packets with expanded headers
- Patent number 8,929,373
- Issue date Jan 6, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Providing error handling support to legacy devices
- Patent number 8,874,976
- Issue date Oct 28, 2014
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Common idle state, active state and credit management for an interface
- Patent number 8,805,926
- Issue date Aug 12, 2014
- Intel Corporation
- Sridhar Lakshmanamurthy
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Aggregating completion messages in a sideband interface
- Patent number 8,711,875
- Issue date Apr 29, 2014
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Supporting multiple channels of a single interface
- Patent number 8,713,234
- Issue date Apr 29, 2014
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller module having independent memory controllers for...
- Patent number 7,308,526
- Issue date Dec 11, 2007
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction for memory
- Patent number 7,203,889
- Issue date Apr 10, 2007
- Intel Corporation
- Alpesh B. Oza
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE
- Publication number 20160132447
- Publication date May 12, 2016
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGEMENT FOR MEMORY ACCESSES IN A SYSTEM-ON-CHIP
- Publication number 20160091957
- Publication date Mar 31, 2016
- Suketu R. Partiwala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR SINGLE-ENDED COMMUNICATION OF TRAN...
- Publication number 20150269109
- Publication date Sep 24, 2015
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENDING PACKETS WITH EXPANDED HEADERS
- Publication number 20150092779
- Publication date Apr 2, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Providing Error Handling Support To Legacy Devices
- Publication number 20150067412
- Publication date Mar 5, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Common Idle State, Active State And Credit Management For An Interface
- Publication number 20150012681
- Publication date Jan 8, 2015
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE
- Publication number 20140258492
- Publication date Sep 11, 2014
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Supporting Multiple Channels Of A Single Interface
- Publication number 20140258578
- Publication date Sep 11, 2014
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing Error Handling Support To Legacy Devices
- Publication number 20130086433
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Aggregating Completion Messages In A Sideband Interface
- Publication number 20130083794
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Common Idle State, Active State And Credit Management For An Interface
- Publication number 20130086139
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Supporting Multiple Channels Of A Single Interface
- Publication number 20130086288
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sending Packets With Expanded Headers
- Publication number 20130083798
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture for supporting high definition content protection decr...
- Publication number 20080159532
- Publication date Jul 3, 2008
- Rohit R. Verma
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Staggering memory requests
- Publication number 20060117114
- Publication date Jun 1, 2006
- Rohit R. Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for supporting memory unaligned writes in a memor...
- Publication number 20060036817
- Publication date Feb 16, 2006
- Alpesh B. Oza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controller
- Publication number 20050273564
- Publication date Dec 8, 2005
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error correction for memory
- Publication number 20050229089
- Publication date Oct 13, 2005
- Alpesh B. Oza
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for high bandwidth random access using dynami...
- Publication number 20050138276
- Publication date Jun 23, 2005
- Intel Corporation
- Muraleedhara H. Navada
- G06 - COMPUTING CALCULATING COUNTING

Verma R. Rohit

Person

Patents Grantslast 30 patents

Sending packets with expanded headers

Method, apparatus and system for single-ended communication of tran...

Systems and an apparatus with a sideband interface interconnecting...

Supporting multiple channels of a single interface

Providing error handling support to legacy devices

Aggregating completion messages in a sideband interface

Common idle state, active state and credit management for an interface

Sending packets with expanded headers

Providing error handling support to legacy devices

Common idle state, active state and credit management for an interface

Aggregating completion messages in a sideband interface

Supporting multiple channels of a single interface

Memory controller module having independent memory controllers for...

Error correction for memory

Patents Applicationslast 30 patents

AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE

POWER MANAGEMENT FOR MEMORY ACCESSES IN A SYSTEM-ON-CHIP

METHOD, APPARATUS AND SYSTEM FOR SINGLE-ENDED COMMUNICATION OF TRAN...

SENDING PACKETS WITH EXPANDED HEADERS

Providing Error Handling Support To Legacy Devices

Common Idle State, Active State And Credit Management For An Interface

AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE

Supporting Multiple Channels Of A Single Interface

Providing Error Handling Support To Legacy Devices

Aggregating Completion Messages In A Sideband Interface

Common Idle State, Active State And Credit Management For An Interface

Supporting Multiple Channels Of A Single Interface

Sending Packets With Expanded Headers

Architecture for supporting high definition content protection decr...

Staggering memory requests

Method and system for supporting memory unaligned writes in a memor...

Memory controller

Error correction for memory

Methods and apparatus for high bandwidth random access using dynami...