Veronica ALARCON

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Enhanced recovery mechanisms
- Patent number 9,542,267
- Issue date Jan 10, 2017
- Broadcom Corporation
- Walid Nabhane
- G05 - CONTROLLING REGULATING
Information Patent Grant
Clock domain crossing serial interface
- Patent number 9,448,878
- Issue date Sep 20, 2016
- Broadcom Corporation
- Veronica Alarcon
- G05 - CONTROLLING REGULATING
Information Patent Grant
Power mode register reduction and power rail bring up enhancement
- Patent number 9,430,323
- Issue date Aug 30, 2016
- Broadcom Corporation
- Chih-Tsung Hsieh
- G05 - CONTROLLING REGULATING
Information Patent Grant
Dynamic power profiling
- Patent number 9,342,400
- Issue date May 17, 2016
- Broadcom Corporation
- Walid Nabhane
- G05 - CONTROLLING REGULATING
Information Patent Grant
Electronics device capable of efficient communication between compo...
- Patent number 9,225,343
- Issue date Dec 29, 2015
- Broadcom Corporation
- Love Kothari
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock domain crossing serial interface, direct latching, and respon...
- Patent number 8,996,736
- Issue date Mar 31, 2015
- Broadcom Corporation
- Veronica Alarcon
- G05 - CONTROLLING REGULATING
Information Patent Grant
Integrated circuit allowing to test a power management unit based o...
- Patent number 8,856,559
- Issue date Oct 7, 2014
- Broadcom Corporation
- Veronica Alarcon
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CLOCK DOMAIN CROSSING SERIAL INTERFACE
- Publication number 20150186209
- Publication date Jul 2, 2015
- BROADCOM CORPORATION
- Veronica ALARCON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC POWER PROFILING
- Publication number 20140218011
- Publication date Aug 7, 2014
- Walid Nabhane
- G01 - MEASURING TESTING
Information Patent Application
POWER MODE REGISTER REDUCTION AND POWER RAIL BRING UP ENHANCEMENT
- Publication number 20140223153
- Publication date Aug 7, 2014
- Chih-Tsung Hsieh
- G01 - MEASURING TESTING
Information Patent Application
ENHANCED RECOVERY MECHANISMS
- Publication number 20140218078
- Publication date Aug 7, 2014
- Walid Nabhane
- G01 - MEASURING TESTING
Information Patent Application
CLOCK DOMAIN CROSSING SERIAL INTERFACE, DIRECT LATCHING, AND RESPON...
- Publication number 20140223031
- Publication date Aug 7, 2014
- Veronica Alarcon
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHOD TO COMBINE PIN FUNCTIONALITY IN AN INTEGRATED...
- Publication number 20130082764
- Publication date Apr 4, 2013
- BROADCOM CORPORATION
- Paul Penzes
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONICS DEVICE CAPABLE OF EFFICIENT COMMUNICATION BETWEEN COMPO...
- Publication number 20130044844
- Publication date Feb 21, 2013
- BROADCOM CORPORATION
- Love KOTHARI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT ALLOWING FOR TESTING AND ISOLATION OF INTEGRATED...
- Publication number 20130047000
- Publication date Feb 21, 2013
- BROADCOM CORPORATION
- Veronica ALARCON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Device authentication system and method
- Publication number 20030120922
- Publication date Jun 26, 2003
- Fairchild Semiconductor Corporation
- NI Sun
- G06 - COMPUTING CALCULATING COUNTING

Veronica ALARCON

Person

Patents Grantslast 30 patents

Enhanced recovery mechanisms

Clock domain crossing serial interface

Power mode register reduction and power rail bring up enhancement

Dynamic power profiling

Electronics device capable of efficient communication between compo...

Clock domain crossing serial interface, direct latching, and respon...

Integrated circuit allowing to test a power management unit based o...

Patents Applicationslast 30 patents

CLOCK DOMAIN CROSSING SERIAL INTERFACE

DYNAMIC POWER PROFILING

POWER MODE REGISTER REDUCTION AND POWER RAIL BRING UP ENHANCEMENT

ENHANCED RECOVERY MECHANISMS

CLOCK DOMAIN CROSSING SERIAL INTERFACE, DIRECT LATCHING, AND RESPON...

APPARATUS AND METHOD TO COMBINE PIN FUNCTIONALITY IN AN INTEGRATED...

ELECTRONICS DEVICE CAPABLE OF EFFICIENT COMMUNICATION BETWEEN COMPO...

INTEGRATED CIRCUIT ALLOWING FOR TESTING AND ISOLATION OF INTEGRATED...

Device authentication system and method