Vicente Enrique Chung

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
System bus structure for large L2 cache array topology with differe...
- Patent number 8,015,358
- Issue date Sep 6, 2011
- International Business Machines Corporation
- Vicente Enrique Chung
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System bus structure for large L2 cache array topology with differe...
- Patent number 7,793,048
- Issue date Sep 7, 2010
- International Business Machines Corporation
- Vicente Enrique Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Request and combined response broadcasting to processors coupled to...
- Patent number 7,627,738
- Issue date Dec 1, 2009
- International Business Machines Corporation
- Vicente E. Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing system with backplane and processor books configura...
- Patent number 7,526,631
- Issue date Apr 28, 2009
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System bus structure for large L2 cache array topology with differe...
- Patent number 7,469,318
- Issue date Dec 23, 2008
- International Business Machines Corporation
- Vicente Enrique Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communication link control among inter-coupled multiple processing...
- Patent number 7,380,102
- Issue date May 27, 2008
- International Business Machines Corporation
- Vicente E. Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System bus read data transfers with data ordering control bits
- Patent number 7,308,536
- Issue date Dec 11, 2007
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor data processing system having scalable data intercon...
- Patent number 7,308,558
- Issue date Dec 11, 2007
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor data processing system having a data routing mechani...
- Patent number 7,007,128
- Issue date Feb 28, 2006
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System bus read data transfers with data ordering control bits
- Patent number 6,874,063
- Issue date Mar 29, 2005
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Robust system bus recovery
- Patent number 6,865,695
- Issue date Mar 8, 2005
- International Business Machines Corpoation
- Jody Bern Joyner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for high performance transmission of ordered p...
- Patent number 6,581,116
- Issue date Jun 17, 2003
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System bus read data transfers with bus utilization based data orde...
- Patent number 6,535,957
- Issue date Mar 18, 2003
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error recovery mechanism for a high-performance interconnect
- Patent number 6,487,679
- Issue date Nov 26, 2002
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System bus read address operations with data ordering preference hi...
- Patent number 6,360,297
- Issue date Mar 19, 2002
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System bus read address operations with data ordering preference hi...
- Patent number 6,349,360
- Issue date Feb 19, 2002
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM BUS STRUCTURE FOR LARGE L2 CACHE ARRAY TOPOLOGY WITH DIFFERE...
- Publication number 20090006759
- Publication date Jan 1, 2009
- Vicente Enrique Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM BUS STRUCTURE FOR LARGE L2 CACHE ARRAY TOPOLOGY WITH DIFFERE...
- Publication number 20090006758
- Publication date Jan 1, 2009
- Vicente Enrique Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING SYSTEM WITH BACKPLANE AND PROCESSOR BOOKS CONFIGURA...
- Publication number 20080209163
- Publication date Aug 28, 2008
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING SYSTEM, METHOD AND INTERCONNECT FABRIC SUPPORTING H...
- Publication number 20080162872
- Publication date Jul 3, 2008
- VICENTE E. CHUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data processing system, method and interconnect fabric supporting h...
- Publication number 20070073998
- Publication date Mar 29, 2007
- Vicente E. Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System bus structure for large L2 cache array topology with differe...
- Publication number 20060179222
- Publication date Aug 10, 2006
- Vicente Enrique Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data processing system, method and interconnect fabric having a par...
- Publication number 20060179197
- Publication date Aug 10, 2006
- International Business Machines Corporation
- Vicente E. Chung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System bus read data transfers with data ordering control bits
- Publication number 20050193174
- Publication date Sep 1, 2005
- IBM CORPORATION
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiprocessor data processing system having scalable data intercon...
- Publication number 20050149692
- Publication date Jul 7, 2005
- International Business Machines Corp.
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiprocessor data processing system having a data routing mechani...
- Publication number 20050149660
- Publication date Jul 7, 2005
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor book for building large scalable processor systems
- Publication number 20040236891
- Publication date Nov 25, 2004
- International Business Machines Corporation
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data processing system having novel interconnect for supporting bot...
- Publication number 20040215926
- Publication date Oct 28, 2004
- International Business Machines Corp.
- Ravi Kumar Arimilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Robust system bus recovery
- Publication number 20030033555
- Publication date Feb 13, 2003
- International Business Machines Corporation
- Jody Bern Joyner
- G06 - COMPUTING CALCULATING COUNTING

Vicente Enrique Chung

Person

Patents Grantslast 30 patents

System bus structure for large L2 cache array topology with differe...

System bus structure for large L2 cache array topology with differe...

Request and combined response broadcasting to processors coupled to...

Data processing system with backplane and processor books configura...

System bus structure for large L2 cache array topology with differe...

Communication link control among inter-coupled multiple processing...

System bus read data transfers with data ordering control bits

Multiprocessor data processing system having scalable data intercon...

Multiprocessor data processing system having a data routing mechani...

System bus read data transfers with data ordering control bits

Robust system bus recovery

Method and apparatus for high performance transmission of ordered p...

System bus read data transfers with bus utilization based data orde...

Error recovery mechanism for a high-performance interconnect

System bus read address operations with data ordering preference hi...

System bus read address operations with data ordering preference hi...

Patents Applicationslast 30 patents

SYSTEM BUS STRUCTURE FOR LARGE L2 CACHE ARRAY TOPOLOGY WITH DIFFERE...

SYSTEM BUS STRUCTURE FOR LARGE L2 CACHE ARRAY TOPOLOGY WITH DIFFERE...

DATA PROCESSING SYSTEM WITH BACKPLANE AND PROCESSOR BOOKS CONFIGURA...

DATA PROCESSING SYSTEM, METHOD AND INTERCONNECT FABRIC SUPPORTING H...

Data processing system, method and interconnect fabric supporting h...

System bus structure for large L2 cache array topology with differe...

Data processing system, method and interconnect fabric having a par...

System bus read data transfers with data ordering control bits

Multiprocessor data processing system having scalable data intercon...

Multiprocessor data processing system having a data routing mechani...

Processor book for building large scalable processor systems

Data processing system having novel interconnect for supporting bot...

Robust system bus recovery