Victor Moroz

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Adaptive row patterns for custom-tiled placement fabrics for mixed...
- Patent number 12,086,523
- Issue date Sep 10, 2024
- Synopsys, Inc.
- Deepak Dattatraya Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-limiting manufacturing techniques to prevent electrical shorts...
- Patent number 12,080,608
- Issue date Sep 3, 2024
- Synopsys, Inc.
- Xi-Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Josephson junction structures
- Patent number 12,041,858
- Issue date Jul 16, 2024
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power routing for 2.5D or 3D integrated circuits including a buried...
- Patent number 11,984,384
- Issue date May 14, 2024
- Synopsys, Inc.
- Xi-Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power harvesting for integrated circuits
- Patent number 11,937,507
- Issue date Mar 19, 2024
- Synopsys, Inc.
- Victor Moroz
Information Patent Grant
Forming a wrap-around contact to connect a source or drain epitaxia...
- Patent number 11,915,984
- Issue date Feb 27, 2024
- Synopsys, Inc.
- Xi-Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CFET SRAM cell utilizing 8 transistors
- Patent number 11,894,049
- Issue date Feb 6, 2024
- Synopsys, Inc.
- Plamen Asenov
- G11 - INFORMATION STORAGE
Information Patent Grant
CFET architecture for balancing logic library and SRAM bitcell
- Patent number 11,837,280
- Issue date Dec 5, 2023
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fin patterning to reduce fin collapse and transistor leakage
- Patent number 11,776,816
- Issue date Oct 3, 2023
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Epitaxial growth of source and drain materials in a complementary f...
- Patent number 11,742,247
- Issue date Aug 29, 2023
- Synopsys, Inc.
- Xi-Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication technique for forming ultra-high density integrated cir...
- Patent number 11,710,634
- Issue date Jul 25, 2023
- Synopsys, Inc.
- Xi-Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electro-thermal method to manufacture monocrystalline vertically or...
- Patent number 11,521,985
- Issue date Dec 6, 2022
- Synopsys, Inc.
- Salvatore Amoroso
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Josephson junction structures
- Patent number 11,489,102
- Issue date Nov 1, 2022
- Synopsys, Inc.
- Jamil Kawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Josephson junction structures
- Patent number 11,342,492
- Issue date May 24, 2022
- Synopsys, Inc.
- Jamil Kawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Crystal orientation engineering to achieve consistent nanowire shapes
- Patent number 11,264,458
- Issue date Mar 1, 2022
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adaptive parallelization for multi-scale simulation
- Patent number 11,249,813
- Issue date Feb 15, 2022
- Synopsys, Inc.
- Stephen Lee Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement and routing of cells using cell-level layout-dependent st...
- Patent number 11,188,699
- Issue date Nov 30, 2021
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power harvesting for integrated circuits
- Patent number 11,177,317
- Issue date Nov 16, 2021
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Crystal orientation engineering to achieve consistent nanowire shapes
- Patent number 11,139,402
- Issue date Oct 5, 2021
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Magnetoresistive random access memory (MRAM) bit cell with a narrow...
- Patent number 11,133,045
- Issue date Sep 28, 2021
- Synopsys, Inc.
- Jamil Kawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
First principles design automation tool
- Patent number 11,068,631
- Issue date Jul 20, 2021
- Synopsys, Inc.
- Yong-Seog Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FinFET cell architecture with insulator structure
- Patent number 10,990,722
- Issue date Apr 27, 2021
- Synopsys, Inc.
- Jamil Kawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Substrates and transistors with 2D material channels on 3D geometries
- Patent number 10,950,736
- Issue date Mar 16, 2021
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simulation scaling with DFT and non-DFT
- Patent number 10,831,957
- Issue date Nov 10, 2020
- Synopsys, Inc.
- Jie Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nano-wire resistance model
- Patent number 10,776,552
- Issue date Sep 15, 2020
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping intermediate material properties to target properties to sc...
- Patent number 10,776,560
- Issue date Sep 15, 2020
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FinFET with heterojunction and improved channel control
- Patent number 10,756,212
- Issue date Aug 25, 2020
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for floating or applying voltage to a well of...
- Patent number 10,741,538
- Issue date Aug 11, 2020
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Estimation of effective channel length for FinFETs and nano-wires
- Patent number 10,706,209
- Issue date Jul 7, 2020
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip heating and self-annealing in FinFETs with anti-punch-throu...
- Patent number 10,699,914
- Issue date Jun 30, 2020
- Synopsys, Inc.
- Hiu Yung Wong
- B82 - NANO-TECHNOLOGY

Patents Applicationslast 30 patents

Information Patent Application
Power Routing for 2.5D or 3D Integrated Circuits Including a Buried...
- Publication number 20240258206
- Publication date Aug 1, 2024
- Synopsys, Inc.
- Xi-Wei LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMING A WRAP-AROUND CONTACT TO CONNECT A SOURCE OR DRAIN EPITAXIA...
- Publication number 20230163032
- Publication date May 25, 2023
- Synopsys, Inc.
- Xi-Wei LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION TECHNIQUE FOR FORMING ULTRA-HIGH DENSITY INTEGRATED CIR...
- Publication number 20230154751
- Publication date May 18, 2023
- Synopsys, Inc.
- XI-WEI LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER ROUTING FOR 2.5D OR 3D INTEGRATED CIRCUITS
- Publication number 20230074159
- Publication date Mar 9, 2023
- Synopsys, Inc.
- Xi-Wei LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INPUT/OUTPUT DEVICES THAT ARE COMPATIBLE WITH GATE-ALL-AROUND TECHN...
- Publication number 20230023073
- Publication date Jan 26, 2023
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ISOLATING ION IMPLANTATION OF SILICON CHANNELS FOR INTEGRATED CIRCU...
- Publication number 20220302284
- Publication date Sep 22, 2022
- Synopsys, Inc.
- Salvatore Maria Amoroso
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADAPTIVE ROW PATTERNS FOR CUSTOM-TILED PLACEMENT FABRICS FOR MIXED...
- Publication number 20220180037
- Publication date Jun 9, 2022
- Synopsys, Inc.
- Deepak Dattatraya SHERLEKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIN PATTERNING TO REDUCE FIN COLLAPSE AND TRANSISTOR LEAKAGE
- Publication number 20220172953
- Publication date Jun 2, 2022
- Synopsys, Inc.
- VICTOR MOROZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MIXED DIFFUSION BREAK FOR CELL DESIGN
- Publication number 20220085018
- Publication date Mar 17, 2022
- Synopsys, Inc.
- Deepak Dattatraya Sherlekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER HARVESTING FOR INTEGRATED CIRCUITS
- Publication number 20220069007
- Publication date Mar 3, 2022
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL GROWTH OF SOURCE AND DRAIN MATERIALS IN A COMPLEMENTARY F...
- Publication number 20220020646
- Publication date Jan 20, 2022
- Synopsys, Inc.
- Xi-Wei LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-LIMITING MANUFACTURING TECHNIQUES TO PREVENT ELECTRICAL SHORTS...
- Publication number 20220020647
- Publication date Jan 20, 2022
- Synopsys, Inc.
- Xi-Wei LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRO-THERMAL METHOD TO MANUFACTURE MONOCRYSTALLINE VERTICALLY OR...
- Publication number 20210249437
- Publication date Aug 12, 2021
- Synopsys, Inc.
- Salvatore AMOROSO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CRYSTAL ORIENTATION ENGINEERING TO ACHIEVE CONSISTENT NANOWIRE SHAPES
- Publication number 20200373388
- Publication date Nov 26, 2020
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLACEMENT AND ROUTING OF CELLS USING CELL-LEVEL LAYOUT-DEPENDENT ST...
- Publication number 20200184136
- Publication date Jun 11, 2020
- Synopsys, Inc.
- Victor MOROZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mapping Intermediate Material Properties to Target Properties to Sc...
- Publication number 20200089841
- Publication date Mar 19, 2020
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive Parallelization For Multi-scale Simulation
- Publication number 20200089543
- Publication date Mar 19, 2020
- Synopsys, Inc.
- STEPHEN LEE SMITH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Estimation of Effective Channel Length for FinFets and Nano-Wires
- Publication number 20200004922
- Publication date Jan 2, 2020
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUBSTRATES AND TRANSISTORS WITH 2D MATERIAL CHANNELS ON 3D GEOMETRIES
- Publication number 20200006578
- Publication date Jan 2, 2020
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
First Principles Design Automation Tool
- Publication number 20190362042
- Publication date Nov 28, 2019
- Synopsys, Inc.
- Yong-Seog Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhancing Memory Yield and Performance Through Utilizing Nanowire S...
- Publication number 20190355437
- Publication date Nov 21, 2019
- Synopsys, Inc.
- JAMIL KAWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRYSTAL ORIENTATION ENGINEERING TO ACHIEVE CONSISTENT NANOWIRE SHAPES
- Publication number 20190348541
- Publication date Nov 14, 2019
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Logic Timing and Reliability Repair for Nanowire Circuits
- Publication number 20190333600
- Publication date Oct 31, 2019
- Synopsys, Inc.
- JAMIL KAWA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Atomic Scale Grid for Modeling Semiconductor Structures and Fabrica...
- Publication number 20190147123
- Publication date May 16, 2019
- Synopsys, Inc.
- Victor Moroz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Finfet with Heterojunction and Improved Channel Control
- Publication number 20190043987
- Publication date Feb 7, 2019
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLACEMENT AND ROUTING OF CELLS USING CELL-LEVEL LAYOUT-DEPENDENT ST...
- Publication number 20180314783
- Publication date Nov 1, 2018
- Synopsys, Inc.
- Victor MOROZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computationally Efficient Nano-Scale Conductor Resistance Model
- Publication number 20180253524
- Publication date Sep 6, 2018
- Synopsys, Inc.
- Karim El Sayed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automated Resistance and Capacitance Extraction and Netlist Generat...
- Publication number 20180239857
- Publication date Aug 23, 2018
- Synopsys, Inc.
- Zudian Qin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus with Channel Stop Doped Devices
- Publication number 20180226301
- Publication date Aug 9, 2018
- Synopsys, Inc.
- VICTOR MOROZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Substrates and Transistors with 2D Material Channels on 3D Geometries
- Publication number 20180182898
- Publication date Jun 28, 2018
- Synopsys, Inc.
- Victor Moroz
- H01 - BASIC ELECTRIC ELEMENTS

Victor Moroz

Person

Patents Grantslast 30 patents

Adaptive row patterns for custom-tiled placement fabrics for mixed...

Self-limiting manufacturing techniques to prevent electrical shorts...

Josephson junction structures

Power routing for 2.5D or 3D integrated circuits including a buried...

Power harvesting for integrated circuits

Forming a wrap-around contact to connect a source or drain epitaxia...

CFET SRAM cell utilizing 8 transistors

CFET architecture for balancing logic library and SRAM bitcell

Fin patterning to reduce fin collapse and transistor leakage

Epitaxial growth of source and drain materials in a complementary f...

Fabrication technique for forming ultra-high density integrated cir...

Electro-thermal method to manufacture monocrystalline vertically or...

Josephson junction structures

Josephson junction structures

Crystal orientation engineering to achieve consistent nanowire shapes

Adaptive parallelization for multi-scale simulation

Placement and routing of cells using cell-level layout-dependent st...

Power harvesting for integrated circuits

Crystal orientation engineering to achieve consistent nanowire shapes

Magnetoresistive random access memory (MRAM) bit cell with a narrow...

First principles design automation tool

FinFET cell architecture with insulator structure

Substrates and transistors with 2D material channels on 3D geometries

Simulation scaling with DFT and non-DFT

Nano-wire resistance model

Mapping intermediate material properties to target properties to sc...

FinFET with heterojunction and improved channel control

Method and apparatus for floating or applying voltage to a well of...

Estimation of effective channel length for FinFETs and nano-wires

On-chip heating and self-annealing in FinFETs with anti-punch-throu...

Patents Applicationslast 30 patents

Power Routing for 2.5D or 3D Integrated Circuits Including a Buried...

FORMING A WRAP-AROUND CONTACT TO CONNECT A SOURCE OR DRAIN EPITAXIA...

FABRICATION TECHNIQUE FOR FORMING ULTRA-HIGH DENSITY INTEGRATED CIR...

POWER ROUTING FOR 2.5D OR 3D INTEGRATED CIRCUITS

INPUT/OUTPUT DEVICES THAT ARE COMPATIBLE WITH GATE-ALL-AROUND TECHN...

ISOLATING ION IMPLANTATION OF SILICON CHANNELS FOR INTEGRATED CIRCU...

ADAPTIVE ROW PATTERNS FOR CUSTOM-TILED PLACEMENT FABRICS FOR MIXED...

FIN PATTERNING TO REDUCE FIN COLLAPSE AND TRANSISTOR LEAKAGE

MIXED DIFFUSION BREAK FOR CELL DESIGN

POWER HARVESTING FOR INTEGRATED CIRCUITS

EPITAXIAL GROWTH OF SOURCE AND DRAIN MATERIALS IN A COMPLEMENTARY F...

SELF-LIMITING MANUFACTURING TECHNIQUES TO PREVENT ELECTRICAL SHORTS...

ELECTRO-THERMAL METHOD TO MANUFACTURE MONOCRYSTALLINE VERTICALLY OR...

CRYSTAL ORIENTATION ENGINEERING TO ACHIEVE CONSISTENT NANOWIRE SHAPES

PLACEMENT AND ROUTING OF CELLS USING CELL-LEVEL LAYOUT-DEPENDENT ST...

Mapping Intermediate Material Properties to Target Properties to Sc...

Adaptive Parallelization For Multi-scale Simulation

Estimation of Effective Channel Length for FinFets and Nano-Wires

SUBSTRATES AND TRANSISTORS WITH 2D MATERIAL CHANNELS ON 3D GEOMETRIES

First Principles Design Automation Tool

Enhancing Memory Yield and Performance Through Utilizing Nanowire S...

CRYSTAL ORIENTATION ENGINEERING TO ACHIEVE CONSISTENT NANOWIRE SHAPES

Logic Timing and Reliability Repair for Nanowire Circuits

Atomic Scale Grid for Modeling Semiconductor Structures and Fabrica...

Finfet with Heterojunction and Improved Channel Control

PLACEMENT AND ROUTING OF CELLS USING CELL-LEVEL LAYOUT-DEPENDENT ST...

Computationally Efficient Nano-Scale Conductor Resistance Model

Automated Resistance and Capacitance Extraction and Netlist Generat...

Method and Apparatus with Channel Stop Doped Devices

Substrates and Transistors with 2D Material Channels on 3D Geometries