Victor Torres

Person

Irving, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for providing a dual via architecture for thin fi...
- Patent number 7,960,240
- Issue date Jun 14, 2011
- National Semiconductor Corporation
- Rodney Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for providing a buried thin film resistor having...
- Patent number 7,808,048
- Issue date Oct 5, 2010
- National Semiconductor Corporation
- Rodney Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for faceting a masking layer in a plasma etch to...
- Patent number 7,585,775
- Issue date Sep 8, 2009
- National Semiconductor Corporation
- Thomas Bold
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for faceting via top corners to improve metal fill
- Patent number 7,456,097
- Issue date Nov 25, 2008
- National Semiconductor Corporation
- Rodney Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for providing a dual via architecture for thin fi...
- Patent number 7,410,879
- Issue date Aug 12, 2008
- National Semiconductor Corporation
- Rodney Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for providing a buried thin film resistor having...
- Patent number 7,332,403
- Issue date Feb 19, 2008
- National Semiconductor Corporation
- Rodney Hill
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for selectively modifying a wet etch rate in a la...
- Patent number 7,172,973
- Issue date Feb 6, 2007
- National Semiconductor Corporation
- Richard W. Foote
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for providing a dry-wet-dry etch procedure to cre...
- Patent number 7,115,500
- Issue date Oct 3, 2006
- National Semiconductor Corporation
- Victor M. Torres
- H01 - BASIC ELECTRIC ELEMENTS

Victor Torres

Person

Patents Grantslast 30 patents

System and method for providing a dual via architecture for thin fi...

System and method for providing a buried thin film resistor having...

System and method for faceting a masking layer in a plasma etch to...

System and method for faceting via top corners to improve metal fill

System and method for providing a dual via architecture for thin fi...

System and method for providing a buried thin film resistor having...

System and method for selectively modifying a wet etch rate in a la...

System and method for providing a dry-wet-dry etch procedure to cre...