Vijay Sharma

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Pune, IN

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Patents Grantslast 30 patents

Information Patent Grant
Integrated clock architecture for improved testing
- Patent number 9,251,916
- Issue date Feb 2, 2016
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Ramesh C. Tekumalla
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan circuitry for testing input and output functional paths of an...
- Patent number 8,826,087
- Issue date Sep 2, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Grant
Clock control for reducing timing exceptions in scan testing of an...
- Patent number 8,799,731
- Issue date Aug 5, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT COMPRISING TEST CIRCUITRY FOR TESTING FAN-OUT PA...
- Publication number 20140365838
- Publication date Dec 11, 2014
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
Method for Testing Paths to Pull-Up and Pull-Down of Input/Output Pads
- Publication number 20140304562
- Publication date Oct 9, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
Integrated Clock Architecture for Improved Testing
- Publication number 20140289550
- Publication date Sep 25, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
SCAN TEST CIRCUITRY WITH CONTROL CIRCUITRY CONFIGURED TO SUPPORT A...
- Publication number 20140149812
- Publication date May 29, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING
Information Patent Application
SCAN CIRCUITRY FOR TESTING INPUT AND OUTPUT FUNCTIONAL PATHS OF AN...
- Publication number 20140143621
- Publication date May 22, 2014
- LSI Corporation
- Ramesh C. Tekumalla
- G01 - MEASURING TESTING