Vijay Tayal

Person

Noida, IN

People

Patents Grantslast 30 patents

Information Patent Grant
System for partitioning integrated circuit design based on timing s...
- Patent number 9,292,651
- Issue date Mar 22, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Chetan Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-edge gated clock signal generator
- Patent number 9,176,522
- Issue date Nov 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Amit Kumar Dey
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power inverter circuit
- Patent number 9,166,585
- Issue date Oct 20, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Amit Roy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for reducing power consumption of integrated circuit
- Patent number 9,003,351
- Issue date Apr 7, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Chetan Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing path slack monitoring system
- Patent number 8,887,120
- Issue date Nov 11, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Chetan Verma
- G01 - MEASURING TESTING
Information Patent Grant
MOS transistor with forward bulk-biasing circuit
- Patent number 8,803,591
- Issue date Aug 12, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Amit Roy
- G05 - CONTROLLING REGULATING
Information Patent Grant
System and method for determining power leakage of electronic circu...
- Patent number 8,793,641
- Issue date Jul 29, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Amit Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for reducing leakage power of electronic circuit
- Patent number 8,762,922
- Issue date Jun 24, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Amit Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for reducing power consumption of electronic circuit
- Patent number 8,527,935
- Issue date Sep 3, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Chetan Verma
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DUAL-EDGE GATED CLOCK SIGNAL GENERATOR
- Publication number 20150316950
- Publication date Nov 5, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Amit Kumar Dey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR PARTITIONING INTEGRATED CIRCUIT DESIGN BASED ON TIMING S...
- Publication number 20150248519
- Publication date Sep 3, 2015
- Chetan Verma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER INVERTER CIRCUIT
- Publication number 20150102839
- Publication date Apr 16, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Amit Roy
- H03 - BASIC ELECTRONIC CIRCUITRY

Vijay Tayal

Person

Patents Grantslast 30 patents

System for partitioning integrated circuit design based on timing s...

Dual-edge gated clock signal generator

Low power inverter circuit

System and method for reducing power consumption of integrated circuit

Timing path slack monitoring system

MOS transistor with forward bulk-biasing circuit

System and method for determining power leakage of electronic circu...

System for reducing leakage power of electronic circuit

System for reducing power consumption of electronic circuit

Patents Applicationslast 30 patents

DUAL-EDGE GATED CLOCK SIGNAL GENERATOR

SYSTEM FOR PARTITIONING INTEGRATED CIRCUIT DESIGN BASED ON TIMING S...

LOW POWER INVERTER CIRCUIT