Vijayakrishna J. Vankayala

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Divided quad clock-based inter-die clocking in a three-dimensional...
- Patent number 12,261,613
- Issue date Mar 25, 2025
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Grant
Divided clock transmission in a three-dimensional stacked memory de...
- Patent number 12,176,031
- Issue date Dec 24, 2024
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Grant
Separate inter-die connectors for data and error correction informa...
- Patent number 12,141,084
- Issue date Nov 12, 2024
- Lodestar Licensing Group LLC
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Access command delay using delay locked loop (DLL) circuitry
- Patent number 11,996,149
- Issue date May 28, 2024
- Jason M. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Pre-decoder circuitry
- Patent number 11,967,373
- Issue date Apr 23, 2024
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Grant
Divided quad clock-based inter-die clocking in a three-dimensional...
- Patent number 11,955,981
- Issue date Apr 9, 2024
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Grant
Read operations for a memory array and register
- Patent number 11,887,687
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and method for trimming input buffers based on identifi...
- Patent number 11,810,641
- Issue date Nov 7, 2023
- Micron Technology, Inc.
- Christian N. Mohr
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power area efficient divided clock shifter scheme for high late...
- Patent number 11,762,786
- Issue date Sep 19, 2023
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Separate inter-die connectors for data and error correction informa...
- Patent number 11,755,506
- Issue date Sep 12, 2023
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with a clocking mechanism
- Patent number 11,742,008
- Issue date Aug 29, 2023
- Micron Technology, Inc.
- Jason M. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods of reducing clock domain crossing timing violations, and re...
- Patent number 11,727,979
- Issue date Aug 15, 2023
- Micron Technology, Inc.
- Kallol Mazumder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant through-silicon vias
- Patent number 11,705,429
- Issue date Jul 18, 2023
- Micron Technology, Inc.
- Jason M. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for parity error alert timing interlock and memory devices...
- Patent number 11,487,610
- Issue date Nov 1, 2022
- Micron Technology, Inc.
- William C. Waldrop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Access command delay using delay locked loop (DLL) circuitry
- Patent number 11,380,395
- Issue date Jul 5, 2022
- Micron Technology, Inc.
- Jason M. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Separate inter-die connectors for data and error correction informa...
- Patent number 11,366,772
- Issue date Jun 21, 2022
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CRC error alert synchronization
- Patent number 11,334,426
- Issue date May 17, 2022
- Micron Technology, Inc.
- Thanh K. Mai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing multi-cycle commands in memory devices, and related meth...
- Patent number 11,164,613
- Issue date Nov 2, 2021
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Grant
Detection circuitry to detect a deck of a memory array
- Patent number 11,127,482
- Issue date Sep 21, 2021
- Micron Technology, Inc.
- Bret Addison Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced peak self-refresh current in a memory device
- Patent number 11,094,363
- Issue date Aug 17, 2021
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with a clocking mechanism
- Patent number 11,024,349
- Issue date Jun 1, 2021
- Micron Technology, Inc.
- Jason M. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with an input signal management mechanism
- Patent number 10,896,703
- Issue date Jan 19, 2021
- Micron Technology, Inc.
- Scott E. Smith
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced shifter memory system
- Patent number 10,872,658
- Issue date Dec 22, 2020
- Micron Technology, Inc.
- Jason M. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for parity error synchronization and memory devices and sys...
- Patent number 10,783,980
- Issue date Sep 22, 2020
- Micron Technology, Inc.
- William C. Waldrop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with a signaling mechanism
- Patent number 10,770,116
- Issue date Sep 8, 2020
- Micron Technology
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and method for trimming input buffers based on identifi...
- Patent number 10,714,156
- Issue date Jul 14, 2020
- Micron Technology, Inc.
- Christian N. Mohr
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for command signal delay
- Patent number 10,699,768
- Issue date Jun 30, 2020
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Grant
Command-in-pipeline counter for a memory device
- Patent number 10,684,797
- Issue date Jun 16, 2020
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced peak self-refresh current in a memory device
- Patent number 10,622,052
- Issue date Apr 14, 2020
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with an input signal management mechanism
- Patent number 10,475,488
- Issue date Nov 12, 2019
- Micron Technology, Inc.
- Scott E. Smith
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMATION AND...
- Publication number 20250061067
- Publication date Feb 20, 2025
- Lodestar Licensing Group LLC
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESS COMMAND DELAY USING COMMAND DELAY CIRCUITRY
- Publication number 20240290384
- Publication date Aug 29, 2024
- Lodestar Licensing Group, LLC
- Jason M. Brown
- G11 - INFORMATION STORAGE
Information Patent Application
PRE-DECODER CIRCUITRY
- Publication number 20240265965
- Publication date Aug 8, 2024
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS WITH CALIBRATION INPUT MECHANISM AND METHODS FOR OPERATIN...
- Publication number 20240241671
- Publication date Jul 18, 2024
- Micron Technology, Inc.
- Kevin G. Werhane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ OPERATIONS FOR A MEMORY ARRAY AND REGISTER
- Publication number 20240242746
- Publication date Jul 18, 2024
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Application
DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL...
- Publication number 20240223196
- Publication date Jul 4, 2024
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Application
Asymmetric Read-Write Sequence for Interconnected Dies
- Publication number 20240070093
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Hyun Yoo Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRE-DECODER CIRCUITRY
- Publication number 20230395145
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Application
REPEATER SCHEME FOR INTER-DIE SIGNALS IN MULTI-DIE PACKAGE
- Publication number 20230395566
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTER-DIE SIGNAL LOAD REDUCTION TECHNIQUE IN MULTI-DIE PACKAGE
- Publication number 20230395565
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEPARATE INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMA...
- Publication number 20230376432
- Publication date Nov 23, 2023
- Lodestar Licensing Group, LLC
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIVIDED CLOCK TRANSMISSION IN A THREE-DIMENSIONAL STACKED MEMORY DE...
- Publication number 20230335192
- Publication date Oct 19, 2023
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Application
DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL...
- Publication number 20230336181
- Publication date Oct 19, 2023
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Application
READ OPERATIONS FOR A MEMORY ARRAY AND REGISTER
- Publication number 20230267974
- Publication date Aug 24, 2023
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER AREA EFFICIENT DIVIDED CLOCK SHIFTER SCHEME FOR HIGH LATE...
- Publication number 20230068313
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS OF REDUCING CLOCK DOMAIN CROSSING TIMING VIOLATIONS, AND RE...
- Publication number 20230007872
- Publication date Jan 12, 2023
- Micron Technology, Inc.
- Kallol Mazumder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCESS COMMAND DELAY USING DELAY LOCKED LOOP (DLL) CIRCUITRY
- Publication number 20220328098
- Publication date Oct 13, 2022
- Micron Technology, Inc.
- Jason M. Brown
- G11 - INFORMATION STORAGE
Information Patent Application
SEPARATE INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMA...
- Publication number 20220309012
- Publication date Sep 29, 2022
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANT THROUGH-SILICON VIAS
- Publication number 20220077112
- Publication date Mar 10, 2022
- Micron Technology, Inc.
- Jason M. Brown
- G11 - INFORMATION STORAGE
Information Patent Application
ACCESS COMMAND DELAY USING DELAY LOCKED LOOP (DLL) CIRCUITRY
- Publication number 20220076745
- Publication date Mar 10, 2022
- Micron Technology, Inc.
- Jason M. Brown
- G11 - INFORMATION STORAGE
Information Patent Application
CRC ERROR ALERT SYNCHRONIZATION
- Publication number 20210326200
- Publication date Oct 21, 2021
- Micron Technology, Inc.
- Thanh K. Mai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETECTION CIRCUITRY TO DETECT A DECK OF A MEMORY ARRAY
- Publication number 20210319846
- Publication date Oct 14, 2021
- Micron Technology, Inc.
- Bret Addison Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
SEPARATE INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMA...
- Publication number 20210286739
- Publication date Sep 16, 2021
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH A CLOCKING MECHANISM
- Publication number 20210249058
- Publication date Aug 12, 2021
- Micron Technology, Inc.
- Jason M. Brown
- G11 - INFORMATION STORAGE
Information Patent Application
PROCESSING MULTI-CYCLE COMMANDS IN MEMORY DEVICES, AND RELATED METH...
- Publication number 20210166742
- Publication date Jun 3, 2021
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHOD FOR TRIMMING INPUT BUFFERS BASED ON IDENTIFI...
- Publication number 20200342922
- Publication date Oct 29, 2020
- Micron Technology, Inc.
- Christian N. Mohr
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCED PEAK SELF-REFRESH CURRENT IN A MEMORY DEVICE
- Publication number 20200219557
- Publication date Jul 9, 2020
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMAND-IN-PIPELINE COUNTER FOR A MEMORY DEVICE
- Publication number 20200073589
- Publication date Mar 5, 2020
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHOD FOR TRIMMING INPUT BUFFERS BASED ON IDENTIFI...
- Publication number 20200075067
- Publication date Mar 5, 2020
- Micron Technology, Inc.
- Christian N. Mohr
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
REDUCED PEAK SELF-REFRESH CURRENT IN A MEMORY DEVICE
- Publication number 20200075087
- Publication date Mar 5, 2020
- Micron Technology, Inc.
- Vijayakrishna J. Vankayala
- G06 - COMPUTING CALCULATING COUNTING

Vijayakrishna J. Vankayala

Person

Patents Grantslast 30 patents

Divided quad clock-based inter-die clocking in a three-dimensional...

Divided clock transmission in a three-dimensional stacked memory de...

Separate inter-die connectors for data and error correction informa...

Access command delay using delay locked loop (DLL) circuitry

Pre-decoder circuitry

Divided quad clock-based inter-die clocking in a three-dimensional...

Read operations for a memory array and register

Apparatuses and method for trimming input buffers based on identifi...

Low power area efficient divided clock shifter scheme for high late...

Separate inter-die connectors for data and error correction informa...

Memory device with a clocking mechanism

Methods of reducing clock domain crossing timing violations, and re...

Redundant through-silicon vias

Methods for parity error alert timing interlock and memory devices...

Access command delay using delay locked loop (DLL) circuitry

Separate inter-die connectors for data and error correction informa...

CRC error alert synchronization

Processing multi-cycle commands in memory devices, and related meth...

Detection circuitry to detect a deck of a memory array

Reduced peak self-refresh current in a memory device

Memory device with a clocking mechanism

Memory device with an input signal management mechanism

Reduced shifter memory system

Methods for parity error synchronization and memory devices and sys...

Memory device with a signaling mechanism

Apparatuses and method for trimming input buffers based on identifi...

Apparatuses and methods for command signal delay

Command-in-pipeline counter for a memory device

Reduced peak self-refresh current in a memory device

Memory device with an input signal management mechanism

Patents Applicationslast 30 patents

INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMATION AND...

ACCESS COMMAND DELAY USING COMMAND DELAY CIRCUITRY

PRE-DECODER CIRCUITRY

APPARATUS WITH CALIBRATION INPUT MECHANISM AND METHODS FOR OPERATIN...

READ OPERATIONS FOR A MEMORY ARRAY AND REGISTER

DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL...

Asymmetric Read-Write Sequence for Interconnected Dies

PRE-DECODER CIRCUITRY

REPEATER SCHEME FOR INTER-DIE SIGNALS IN MULTI-DIE PACKAGE

INTER-DIE SIGNAL LOAD REDUCTION TECHNIQUE IN MULTI-DIE PACKAGE

SEPARATE INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMA...

DIVIDED CLOCK TRANSMISSION IN A THREE-DIMENSIONAL STACKED MEMORY DE...

DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL...

READ OPERATIONS FOR A MEMORY ARRAY AND REGISTER

LOW POWER AREA EFFICIENT DIVIDED CLOCK SHIFTER SCHEME FOR HIGH LATE...

METHODS OF REDUCING CLOCK DOMAIN CROSSING TIMING VIOLATIONS, AND RE...

ACCESS COMMAND DELAY USING DELAY LOCKED LOOP (DLL) CIRCUITRY

SEPARATE INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMA...

REDUNDANT THROUGH-SILICON VIAS

ACCESS COMMAND DELAY USING DELAY LOCKED LOOP (DLL) CIRCUITRY

CRC ERROR ALERT SYNCHRONIZATION

DETECTION CIRCUITRY TO DETECT A DECK OF A MEMORY ARRAY

SEPARATE INTER-DIE CONNECTORS FOR DATA AND ERROR CORRECTION INFORMA...

MEMORY DEVICE WITH A CLOCKING MECHANISM

PROCESSING MULTI-CYCLE COMMANDS IN MEMORY DEVICES, AND RELATED METH...

APPARATUSES AND METHOD FOR TRIMMING INPUT BUFFERS BASED ON IDENTIFI...

REDUCED PEAK SELF-REFRESH CURRENT IN A MEMORY DEVICE

COMMAND-IN-PIPELINE COUNTER FOR A MEMORY DEVICE

APPARATUSES AND METHOD FOR TRIMMING INPUT BUFFERS BASED ON IDENTIFI...

REDUCED PEAK SELF-REFRESH CURRENT IN A MEMORY DEVICE