Vikas Chelani

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Noida, IN

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Patents Grantslast 30 patents

Information Patent Grant
Clock delay circuit for chip reset architecture
- Patent number 12,055,989
- Issue date Aug 6, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Ankur Bal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debounce circuit with noise immunity and glitch event tracking
- Patent number 11,177,799
- Issue date Nov 16, 2021
- STMICROELECTRONICS INTERNATIONAL N.V.
- Ankur Bal
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CLOCK DELAY CIRCUIT FOR CHIP RESET ARCHITECTURE
- Publication number 20210286417
- Publication date Sep 16, 2021
- STMicroelectronics International N.V.
- Ankur BAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEBOUNCE CIRCUIT WITH NOISE IMMUNITY AND GLITCH EVENT TRACKING
- Publication number 20210119621
- Publication date Apr 22, 2021
- STMicroelectronics International N.V.
- Ankur Bal
- H03 - BASIC ELECTRONIC CIRCUITRY