Vikram Iyengar

Person

South Burlington, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and structure for multi-core chip product test and selective...
- Patent number 9,557,378
- Issue date Jan 31, 2017
- GLOBALFOUNDRIES Inc.
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for single cell product path delay analysis
- Patent number 9,104,834
- Issue date Aug 11, 2015
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit product yield optimization using the results of...
- Patent number 9,058,034
- Issue date Jun 16, 2015
- International Business Machines Corporation
- Jeanne P. Bickford
- G05 - CONTROLLING REGULATING
Information Patent Grant
Reducing power consumption during manufacturing test of an integrat...
- Patent number 9,043,180
- Issue date May 26, 2015
- International Business Machines Corporation
- Vikram Iyengar
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for single cell product path delay analysis
- Patent number 8,904,329
- Issue date Dec 2, 2014
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation of valid at-speed structural test (ASST) test...
- Patent number 8,825,433
- Issue date Sep 2, 2014
- International Business Machines Corporation
- Konda R. Baalaji
- G01 - MEASURING TESTING
Information Patent Grant
Test path selection and test program generation for performance tes...
- Patent number 8,543,966
- Issue date Sep 24, 2013
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Grant
System yield optimization using the results of integrated circuit c...
- Patent number 8,539,429
- Issue date Sep 17, 2013
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Grant
Clock edge grouping for at-speed test
- Patent number 8,538,718
- Issue date Sep 17, 2013
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Disposition of integrated circuits using performance sort ring osci...
- Patent number 8,490,040
- Issue date Jul 16, 2013
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Grant
Method to test hold path faults using functional clocking
- Patent number 8,230,283
- Issue date Jul 24, 2012
- International Business Machines Corporation
- Pamela S. Gillis
- G01 - MEASURING TESTING
Information Patent Grant
System and method for automatically generating test patterns for at...
- Patent number 8,209,141
- Issue date Jun 26, 2012
- International Business Machines Corporation
- Robert W. Bassett
- G01 - MEASURING TESTING
Information Patent Grant
Hold transition fault model and test generation method
- Patent number 8,181,135
- Issue date May 15, 2012
- International Business Machines Corporation
- Vikram Iyengar
- G01 - MEASURING TESTING
Information Patent Grant
Online multiprocessor system reliability defect testing
- Patent number 8,176,362
- Issue date May 8, 2012
- International Business Machines Corporation
- Monty M Denneau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated test waveform generator (TWG) and customer waveform gene...
- Patent number 7,996,807
- Issue date Aug 9, 2011
- International Business Machines Corporation
- Gary D. Grise
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for generating at-speed structural tests to impro...
- Patent number 7,856,607
- Issue date Dec 21, 2010
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Method of increasing path coverage in transition test generation
- Patent number 7,793,176
- Issue date Sep 7, 2010
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Identifying sequential functional paths for IC testing methods and...
- Patent number 7,784,000
- Issue date Aug 24, 2010
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Design structure for shutting off data capture across asynchronous...
- Patent number 7,779,375
- Issue date Aug 17, 2010
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus and method for selectively implementing launch off scan c...
- Patent number 7,721,170
- Issue date May 18, 2010
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for shutting off data capture across asynchron...
- Patent number 7,685,542
- Issue date Mar 23, 2010
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Grant
IC chip at-functional-speed testing with process coverage evaluation
- Patent number 7,620,921
- Issue date Nov 17, 2009
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing of multiple asynchronous logic domains
- Patent number 7,529,294
- Issue date May 5, 2009
- International Business Machines Corporation
- Gary Douglas Grise
- G01 - MEASURING TESTING
Information Patent Grant
Efficient scan chain insertion using broadcast scan for reduced bit...
- Patent number 7,441,171
- Issue date Oct 21, 2008
- International Business Machines Corporation
- Vikram Iyengar
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR SINGLE CELL PRODUCT PATH DELAY ANALYSIS
- Publication number 20150033199
- Publication date Jan 29, 2015
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR SINGLE CELL PRODUCT PATH DELAY ANALYSIS
- Publication number 20140195995
- Publication date Jul 10, 2014
- International Business Machines Corporation
- Jeanne P. Bickford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT PRODUCT YIELD OPTIMIZATION USING THE RESULTS OF...
- Publication number 20140046466
- Publication date Feb 13, 2014
- International Business Machines Corporation
- Jeanne P. Bickford
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
METHOD AND STRUCTURE FOR MULTI-CORE CHIP PRODUCT TEST AND SELECTIVE...
- Publication number 20140024145
- Publication date Jan 23, 2014
- International Business Machines Corporation
- JEANNE P. BICKFORD
- G01 - MEASURING TESTING
Information Patent Application
REDUCING POWER CONSUMPTION DURING MANUFACTURING TEST OF AN INTEGRAT...
- Publication number 20130211769
- Publication date Aug 15, 2013
- International Business Machines Corporation
- Vikram Iyengar
- G01 - MEASURING TESTING
Information Patent Application
DISPOSITION OF INTEGRATED CIRCUITS USING PERFORMANCE SORT RING OSCI...
- Publication number 20130125076
- Publication date May 16, 2013
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TES...
- Publication number 20130125073
- Publication date May 16, 2013
- International Business Machines Corporation
- Jeanne P. Bickford
- G01 - MEASURING TESTING
Information Patent Application
AUTOMATIC GENERATION OF VALID AT-SPEED STRUCTURAL TEST (ASST) TEST...
- Publication number 20130080108
- Publication date Mar 28, 2013
- International Business Machines Corporation
- Konda R. BAALAJI
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED SCAN ENABLE SWITCHING CIRCUIT
- Publication number 20120176144
- Publication date Jul 12, 2012
- International Business Machines Corporation
- Vikram Iyengar
- G01 - MEASURING TESTING
Information Patent Application
CLOCK EDGE GROUPING FOR AT-SPEED TEST
- Publication number 20120150473
- Publication date Jun 14, 2012
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
METHOD TO TEST HOLD PATH FAULTS USING FUNCTIONAL CLOCKING
- Publication number 20110154141
- Publication date Jun 23, 2011
- International Business Machines Corporation
- Pamela S. Gillis
- G01 - MEASURING TESTING
Information Patent Application
Hold Transition Fault Model and Test Generation Method
- Publication number 20110055650
- Publication date Mar 3, 2011
- International Business Machines Corporation
- Vikram Iyengar
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR AUTOMATICALLY GENERATING TEST PATTERNS FOR AT...
- Publication number 20100235136
- Publication date Sep 16, 2010
- International Business Machines Corporation
- Robert W. Bassett
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENE...
- Publication number 20090265677
- Publication date Oct 22, 2009
- Gary D. Grise
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ONLINE MULTIPROCESSOR SYSTEM RELIABILITY DEFECT TESTING
- Publication number 20090241124
- Publication date Sep 24, 2009
- Monty M. Denneau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INDENTIFYING SEQUENTIAL FUNCTIONAL PATHS FOR IC TESTING METHODS AND...
- Publication number 20090240459
- Publication date Sep 24, 2009
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
CRITICAL PATH SELECTION FOR AT-SPEED TEST
- Publication number 20090150844
- Publication date Jun 11, 2009
- International Business Machines Corporation
- Vikram Iyengar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPRO...
- Publication number 20090119629
- Publication date May 7, 2009
- Gary D. Grise
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR SHUTTING OFF DATA CAPTURE ACROSS ASYNCHRONOUS...
- Publication number 20090102507
- Publication date Apr 23, 2009
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN C...
- Publication number 20090106608
- Publication date Apr 23, 2009
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION
- Publication number 20080270953
- Publication date Oct 30, 2008
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Increasing Path Coverage in Transition Test Generation
- Publication number 20080250279
- Publication date Oct 9, 2008
- International Business Machines Corporation
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR AUTOMATIC TEST PATTERN GENERATION FOR ONE TEST CONSTRAIN...
- Publication number 20080222472
- Publication date Sep 11, 2008
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS FOR SHUTTING OFF DATA CAPTURE ACROSS ASYNCHRON...
- Publication number 20080195905
- Publication date Aug 14, 2008
- Gary D. Grise
- G01 - MEASURING TESTING
Information Patent Application
EFFICIENT SCAN CHAIN INSERTION USING BROADCAST SCAN FOR REDUCED BIT...
- Publication number 20070226564
- Publication date Sep 27, 2007
- Vikram Iyengar
- G01 - MEASURING TESTING
Information Patent Application
TESTING OF MULTIPLE ASYNCHRONOUS LOGIC DOMAINS
- Publication number 20070204194
- Publication date Aug 30, 2007
- Gary Douglas Grise
- G01 - MEASURING TESTING

Vikram Iyengar

Person

Patents Grantslast 30 patents

Method and structure for multi-core chip product test and selective...

Systems and methods for single cell product path delay analysis

Integrated circuit product yield optimization using the results of...

Reducing power consumption during manufacturing test of an integrat...

Systems and methods for single cell product path delay analysis

Automatic generation of valid at-speed structural test (ASST) test...

Test path selection and test program generation for performance tes...

System yield optimization using the results of integrated circuit c...

Clock edge grouping for at-speed test

Disposition of integrated circuits using performance sort ring osci...

Method to test hold path faults using functional clocking

System and method for automatically generating test patterns for at...

Hold transition fault model and test generation method

Online multiprocessor system reliability defect testing

Integrated test waveform generator (TWG) and customer waveform gene...

System and method for generating at-speed structural tests to impro...

Method of increasing path coverage in transition test generation

Identifying sequential functional paths for IC testing methods and...

Design structure for shutting off data capture across asynchronous...

Apparatus and method for selectively implementing launch off scan c...

Method and apparatus for shutting off data capture across asynchron...

IC chip at-functional-speed testing with process coverage evaluation

Testing of multiple asynchronous logic domains

Efficient scan chain insertion using broadcast scan for reduced bit...

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR SINGLE CELL PRODUCT PATH DELAY ANALYSIS

SYSTEMS AND METHODS FOR SINGLE CELL PRODUCT PATH DELAY ANALYSIS

INTEGRATED CIRCUIT PRODUCT YIELD OPTIMIZATION USING THE RESULTS OF...

METHOD AND STRUCTURE FOR MULTI-CORE CHIP PRODUCT TEST AND SELECTIVE...

REDUCING POWER CONSUMPTION DURING MANUFACTURING TEST OF AN INTEGRAT...

DISPOSITION OF INTEGRATED CIRCUITS USING PERFORMANCE SORT RING OSCI...

TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TES...

AUTOMATIC GENERATION OF VALID AT-SPEED STRUCTURAL TEST (ASST) TEST...

AT-SPEED SCAN ENABLE SWITCHING CIRCUIT

CLOCK EDGE GROUPING FOR AT-SPEED TEST

METHOD TO TEST HOLD PATH FAULTS USING FUNCTIONAL CLOCKING

Hold Transition Fault Model and Test Generation Method

SYSTEM AND METHOD FOR AUTOMATICALLY GENERATING TEST PATTERNS FOR AT...

INTEGRATED TEST WAVEFORM GENERATOR (TWG) AND CUSTOMER WAVEFORM GENE...

ONLINE MULTIPROCESSOR SYSTEM RELIABILITY DEFECT TESTING

INDENTIFYING SEQUENTIAL FUNCTIONAL PATHS FOR IC TESTING METHODS AND...

CRITICAL PATH SELECTION FOR AT-SPEED TEST

SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPRO...

DESIGN STRUCTURE FOR SHUTTING OFF DATA CAPTURE ACROSS ASYNCHRONOUS...

APPARATUS AND METHOD FOR SELECTIVELY IMPLEMENTING LAUNCH OFF SCAN C...

IC CHIP AT-FUNCTIONAL-SPEED TESTING WITH PROCESS COVERAGE EVALUATION

Method of Increasing Path Coverage in Transition Test Generation

METHOD FOR AUTOMATIC TEST PATTERN GENERATION FOR ONE TEST CONSTRAIN...

METHOD AND APPARATUS FOR SHUTTING OFF DATA CAPTURE ACROSS ASYNCHRON...

EFFICIENT SCAN CHAIN INSERTION USING BROADCAST SCAN FOR REDUCED BIT...

TESTING OF MULTIPLE ASYNCHRONOUS LOGIC DOMAINS