Vikrant CHAUHAN

Person

Clifton Park, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit methods using single-pin imaginary devices
- Patent number 11,036,913
- Issue date Jun 15, 2021
- Marvell Asia Pte., Ltd.
- Heng Lan Lau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test structures connected with the lowest metallization levels in a...
- Patent number 10,796,973
- Issue date Oct 6, 2020
- GLOBALFOUNDRIES Inc.
- Mankyu Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure leveraging the lowest metallization level of an inte...
- Patent number 10,790,204
- Issue date Sep 29, 2020
- GLOBALFOUNDRIES Inc.
- Mankyu Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit (IC) design systems and methods using single-pin...
- Patent number 10,579,774
- Issue date Mar 3, 2020
- Marvell International Ltd.
- Heng Lan Lau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FDSOI semiconductor device with contact enhancement layer and metho...
- Patent number 10,347,543
- Issue date Jul 9, 2019
- GLOBALFOUNDRIES Inc.
- Peter Baars
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional pattern risk scoring
- Patent number 10,311,186
- Issue date Jun 4, 2019
- GLOBALFOUNDRIES Inc.
- Jaime Bravo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for a high density middle of line flow
- Patent number 10,236,350
- Issue date Mar 19, 2019
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-directional self-aligned multiple patterning
- Patent number 10,199,270
- Issue date Feb 5, 2019
- GLOBALFOUNDRIES Inc.
- Colin Bombardier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
On-chip capacitors with floating islands
- Patent number 10,147,783
- Issue date Dec 4, 2018
- GLOBALFOUNDRIES Inc.
- Atsushi Ogino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level electrical test for optical proximity correction and/or...
- Patent number 10,078,107
- Issue date Sep 18, 2018
- GLOBALFOUNDRIES Inc.
- Jaime Bravo
- G01 - MEASURING TESTING
Information Patent Grant
Multi-polygon constraint decomposition techniques for use in double...
- Patent number 9,465,907
- Issue date Oct 11, 2016
- GLOBALFOUNDRIES Inc.
- Ahmed Hassan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forming merged lines in a metallization layer by replacing sacrific...
- Patent number 9,412,655
- Issue date Aug 9, 2016
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Critical dimension and pattern recognition structures for devices m...
- Patent number 8,932,961
- Issue date Jan 13, 2015
- GLOBALFOUNDRIES Inc.
- Sohan Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor designs for integrated circuits utilizing self-aligned do...
- Patent number 8,856,715
- Issue date Oct 7, 2014
- GLOBALFOUNDRIES Inc.
- Jason Stephens
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT METHODS USING SINGLE-PIN IMAGINARY DEVICES
- Publication number 20200202065
- Publication date Jun 25, 2020
- Marvell International Ltd.
- Heng Lan LAU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST STRUCTURE LEVERAGING THE LOWEST METALLIZATION LEVEL OF AN INTE...
- Publication number 20200152530
- Publication date May 14, 2020
- GLOBALFOUNDRIES INC.
- Mankyu Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TEST STRUCTURES CONNECTED WITH THE LOWEST METALLIZATION LEVELS IN A...
- Publication number 20200152531
- Publication date May 14, 2020
- GLOBALFOUNDRIES INC.
- Mankyu Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT (IC) DESIGN SYSTEMS AND METHODS USING SINGLE-PIN...
- Publication number 20190384885
- Publication date Dec 19, 2019
- GLOBALFOUNDRIES INC.
- Heng Lan Lau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FDSOI SEMICONDUCTOR DEVICE WITH CONTACT ENHANCEMENT LAYER AND METHO...
- Publication number 20190148245
- Publication date May 16, 2019
- GLOBALFOUNDRIES INC.
- Peter Baars
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-DIRECTIONAL SELF-ALIGNED MULTIPLE PATTERNING
- Publication number 20180342421
- Publication date Nov 29, 2018
- GLOBALFOUNDRIES INC.
- Colin Bombardier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ON-CHIP CAPACITORS WITH FLOATING ISLANDS
- Publication number 20180269275
- Publication date Sep 20, 2018
- GLOBALFOUNDRIES INC.
- Atsushi Ogino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A SHALLOW TRENCH ISOLATION STRUCTURE USING A NIT...
- Publication number 20180040505
- Publication date Feb 8, 2018
- GLOBALFOUNDRIES Inc.
- Sandeep Gaan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL PATTERN RISK SCORING
- Publication number 20170293704
- Publication date Oct 12, 2017
- GLOBALFOUNDRIES INC.
- Jaime BRAVO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR A HIGH DENSITY MIDDLE OF LINE FLOW
- Publication number 20170263715
- Publication date Sep 14, 2017
- GLOBALFOUNDRIES Inc.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL ELECTRICAL TEST FOR OPTICAL PROXIMITY CORRECTION AND/OR...
- Publication number 20170115337
- Publication date Apr 27, 2017
- GLOBALFOUNDRIES INC.
- Jaime BRAVO
- G01 - MEASURING TESTING
Information Patent Application
FORMING MERGED LINES IN A METALLIZATION LAYER BY REPLACING SACRIFIC...
- Publication number 20160225666
- Publication date Aug 4, 2016
- GLOBALFOUNDRIES INC.
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-POLYGON CONSTRAINT DECOMPOSITION TECHNIQUES FOR USE IN DOUBLE...
- Publication number 20160026748
- Publication date Jan 28, 2016
- GLOBALFOUNDRIES INC.
- Ahmed Hassan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CRITICAL DIMENSION AND PATTERN RECOGNITION STRUCTURES FOR DEVICES M...
- Publication number 20150050811
- Publication date Feb 19, 2015
- GLOBALFOUNDRIES INC.
- Sohan Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Critical Dimension and Pattern Recognition Structures for Devices M...
- Publication number 20130207108
- Publication date Aug 15, 2013
- GLOBALFOUNDRIES INC.
- Sohan Mehta
- H01 - BASIC ELECTRIC ELEMENTS

Vikrant CHAUHAN

Person

Patents Grantslast 30 patents

Integrated circuit methods using single-pin imaginary devices

Test structures connected with the lowest metallization levels in a...

Test structure leveraging the lowest metallization level of an inte...

Integrated circuit (IC) design systems and methods using single-pin...

FDSOI semiconductor device with contact enhancement layer and metho...

Three-dimensional pattern risk scoring

Method, apparatus and system for a high density middle of line flow

Multi-directional self-aligned multiple patterning

On-chip capacitors with floating islands

Wafer level electrical test for optical proximity correction and/or...

Multi-polygon constraint decomposition techniques for use in double...

Forming merged lines in a metallization layer by replacing sacrific...

Critical dimension and pattern recognition structures for devices m...

Capacitor designs for integrated circuits utilizing self-aligned do...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT METHODS USING SINGLE-PIN IMAGINARY DEVICES

TEST STRUCTURE LEVERAGING THE LOWEST METALLIZATION LEVEL OF AN INTE...

TEST STRUCTURES CONNECTED WITH THE LOWEST METALLIZATION LEVELS IN A...

INTEGRATED CIRCUIT (IC) DESIGN SYSTEMS AND METHODS USING SINGLE-PIN...

FDSOI SEMICONDUCTOR DEVICE WITH CONTACT ENHANCEMENT LAYER AND METHO...

MULTI-DIRECTIONAL SELF-ALIGNED MULTIPLE PATTERNING

ON-CHIP CAPACITORS WITH FLOATING ISLANDS

METHOD FOR FORMING A SHALLOW TRENCH ISOLATION STRUCTURE USING A NIT...

THREE-DIMENSIONAL PATTERN RISK SCORING

METHOD, APPARATUS AND SYSTEM FOR A HIGH DENSITY MIDDLE OF LINE FLOW

WAFER LEVEL ELECTRICAL TEST FOR OPTICAL PROXIMITY CORRECTION AND/OR...

FORMING MERGED LINES IN A METALLIZATION LAYER BY REPLACING SACRIFIC...

MULTI-POLYGON CONSTRAINT DECOMPOSITION TECHNIQUES FOR USE IN DOUBLE...

CRITICAL DIMENSION AND PATTERN RECOGNITION STRUCTURES FOR DEVICES M...

Critical Dimension and Pattern Recognition Structures for Devices M...