Vinay Sadrhalli Nagendra PATEL

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Karnataka, IN

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Patents Grantslast 30 patents

Information Patent Grant
System and method for processor debug using low-bandwidth interface...
- Patent number 12,174,714
- Issue date Dec 24, 2024
- SILICONCH SYSTEMS PVT LTD
- Rakesh Kumar Polasa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for reception of noisy BMC data in USB PD communi...
- Patent number 12,045,109
- Issue date Jul 23, 2024
- SILICONCH SYSTEMS PVT LTD
- Rakesh Kumar Polasa
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR REAL-TIME DEBUGGING OF PROCESSOR
- Publication number 20240126666
- Publication date Apr 18, 2024
- SILICONCH SYSTEMS PVT LTD
- Rakesh Kumar POLASA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR RECEPTION OF NOISY BMC DATA IN USB PD COMMUNI...
- Publication number 20230010655
- Publication date Jan 12, 2023
- SILICONCH SYSTEMS PVT LTD
- Rakesh Kumar POLASA
- G06 - COMPUTING CALCULATING COUNTING