Vincent Philippe Schuppe

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit layout techniques
- Patent number 11,475,200
- Issue date Oct 18, 2022
- ARM Limited
- Yulin Shi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tile-cell interpolation
- Patent number 10,579,775
- Issue date Mar 3, 2020
- ARM Limited
- Vincent Philippe Schuppe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inverter circuitry
- Patent number 10,403,643
- Issue date Sep 3, 2019
- ARM Limited
- Yew Keong Chong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic capacitance balancing
- Patent number 9,570,157
- Issue date Feb 14, 2017
- ARM Limited
- Vincent Philippe Schuppe
- G11 - INFORMATION STORAGE
Information Patent Grant
Improving read stability of a semiconductor memory
- Patent number 8,830,783
- Issue date Sep 9, 2014
- ARM Limited
- Sachin Satish Idgunji
- G11 - INFORMATION STORAGE
Information Patent Grant
Controlling a voltage level of an access signal to reduce access di...
- Patent number 8,611,172
- Issue date Dec 17, 2013
- ARM Limited
- Amaranth Shyanmugam
- G11 - INFORMATION STORAGE
Information Patent Grant
Generating ROM bit cell arrays
- Patent number 8,422,262
- Issue date Apr 16, 2013
- ARM Limited
- Yannick Marc Nevers
- G11 - INFORMATION STORAGE
Information Patent Grant
Generating ROM bit cell arrays
- Patent number 7,961,490
- Issue date Jun 14, 2011
- ARM Limited
- Yannick Marc Nevers
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method of operating such a memory device
- Patent number 7,613,053
- Issue date Nov 3, 2009
- ARM Limited
- Nicolaas Klarinus Johannes van Winkelhoff
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Circuit Layout Techniques
- Publication number 20210383050
- Publication date Dec 9, 2021
- Yulin Shi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TILE-CELL INTERPOLATION
- Publication number 20200019669
- Publication date Jan 16, 2020
- ARM Limited
- Vincent Philippe Schuppe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Inverter Circuitry
- Publication number 20180323215
- Publication date Nov 8, 2018
- ARM Limited
- Yew Keong Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dynamic Capacitance Balancing
- Publication number 20170062043
- Publication date Mar 2, 2017
- ARM Limited
- Vincent Philippe Schuppe
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLING A VOLTAGE LEVEL OF AN ACCESS SIGNAL TO REDUCE ACCESS DI...
- Publication number 20130308407
- Publication date Nov 21, 2013
- ARM Limited
- Amaranth Shyanmugam
- G11 - INFORMATION STORAGE
Information Patent Application
Read stability of a semiconductor memory
- Publication number 20120170390
- Publication date Jul 5, 2012
- ARM Limited
- Sachin Satish Idgunji
- G11 - INFORMATION STORAGE
Information Patent Application
Generating ROM bit cell arrays
- Publication number 20110249481
- Publication date Oct 13, 2011
- ARM Limited
- Yannick Marc Nevers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generating ROM bit cell arrays
- Publication number 20100177544
- Publication date Jul 15, 2010
- ARM Limited
- Yannick Marc Nevers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory device and method of operating such a memory device
- Publication number 20090135663
- Publication date May 28, 2009
- ARM Limited
- Nicolaas Klarinus Johannes van Winkelhoff
- G11 - INFORMATION STORAGE

Vincent Philippe Schuppe

Person

Patents Grantslast 30 patents

Circuit layout techniques

Tile-cell interpolation

Inverter circuitry

Dynamic capacitance balancing

Improving read stability of a semiconductor memory

Controlling a voltage level of an access signal to reduce access di...

Generating ROM bit cell arrays

Generating ROM bit cell arrays

Memory device and method of operating such a memory device

Patents Applicationslast 30 patents

Circuit Layout Techniques

TILE-CELL INTERPOLATION

Inverter Circuitry

Dynamic Capacitance Balancing

CONTROLLING A VOLTAGE LEVEL OF AN ACCESS SIGNAL TO REDUCE ACCESS DI...

Read stability of a semiconductor memory

Generating ROM bit cell arrays

Generating ROM bit cell arrays

Memory device and method of operating such a memory device