Vipul V. Mehta

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hydrophobic feature to control adhesive flow
- Patent number 12,130,482
- Issue date Oct 29, 2024
- Intel Corporation
- Bassam Ziadeh
- G02 - OPTICS
Information Patent Grant
Protruding SN substrate features for epoxy flow control
- Patent number 12,009,271
- Issue date Jun 11, 2024
- Intel Corporation
- Edvin Cetegen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Barrier structures for underfill containment
- Patent number 12,002,727
- Issue date Jun 4, 2024
- Intel Corporation
- Ziyin Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with underfill containment barrier
- Patent number 11,935,805
- Issue date Mar 19, 2024
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro-electronic package with substrate protrusion to facilitate di...
- Patent number 11,776,821
- Issue date Oct 3, 2023
- Intel Corporation
- Ziyin Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High thermal conductivity, high modulus structure within a mold mat...
- Patent number 11,749,585
- Issue date Sep 5, 2023
- Intel Corporation
- Yiqun Bai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trenches in wafer level packages for improvements in warpage reliab...
- Patent number 11,688,634
- Issue date Jun 27, 2023
- Intel Corporation
- Vipul Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor die package with warpage management and process for f...
- Patent number 11,676,876
- Issue date Jun 13, 2023
- Intel Corporation
- Ziyin Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with underfill containment barrier
- Patent number 11,664,290
- Issue date May 30, 2023
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having wafer-level active die and external di...
- Patent number 11,545,441
- Issue date Jan 3, 2023
- Intel Corporation
- Vipul Vijay Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro-electronic package with substrate protrusion to facilitate di...
- Patent number 11,282,717
- Issue date Mar 22, 2022
- Intel Corporation
- Ziyin Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with underfill containment barrier
- Patent number 11,158,558
- Issue date Oct 26, 2021
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having wafer-level active die and external di...
- Patent number 10,910,317
- Issue date Feb 2, 2021
- Intel Corporation
- Vipul Vijay Mehta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device package
- Patent number 10,403,578
- Issue date Sep 3, 2019
- Intel Corporation
- Digvijay A. Raorane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic package assembly with compact die placement
- Patent number 10,373,888
- Issue date Aug 6, 2019
- Intel Corporation
- Eric J. Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package, and a method for forming a semiconductor pac...
- Patent number 10,290,592
- Issue date May 14, 2019
- Intel Corporation
- John J Beatty
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques and configurations for surface treatment of an integrate...
- Patent number 8,895,365
- Issue date Nov 25, 2014
- Intel Corporation
- Suriyakala Ramalingam
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC

Patents Applicationslast 30 patents

Information Patent Application
HYDROPHOBIC FEATURE TO CONTROL ADHESIVE FLOW
- Publication number 20240402445
- Publication date Dec 5, 2024
- Intel Corporation
- Bassam ZIADEH
- G02 - OPTICS
Information Patent Application
PROTRUDING SN SUBSTRATE FEATURES FOR EPOXY FLOW CONTROL
- Publication number 20240258183
- Publication date Aug 1, 2024
- Intel Corporation
- Edvin CETEGEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20240186202
- Publication date Jun 6, 2024
- Intel Corporation
- Rahul JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BARRIER ENABLED CUF AND MOLD PROCESS FOR MULTI-CHIP PACKAGING
- Publication number 20240153837
- Publication date May 9, 2024
- Intel Corporation
- Ziyin LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20230245940
- Publication date Aug 3, 2023
- Intel Corporation
- Rahul JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYDROPHOBIC FEATURE TO CONTROL ADHESIVE FLOW
- Publication number 20220196937
- Publication date Jun 23, 2022
- Intel Corporation
- Bassam ZIADEH
- G02 - OPTICS
Information Patent Application
MICRO-ELECTRONIC PACKAGE WITH SUBSTRATE PROTRUSION TO FACILITATE DI...
- Publication number 20220165585
- Publication date May 26, 2022
- Intel Corporation
- Ziyin LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20210391232
- Publication date Dec 16, 2021
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH THERMAL CONDUCTIVITY, HIGH MODULUS STRUCTURE WITHIN A MOLD MAT...
- Publication number 20210272878
- Publication date Sep 2, 2021
- Intel Corporation
- Yiqun Bai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BARRIER STRUCTURES FOR UNDERFILL CONTAINMENT
- Publication number 20210249322
- Publication date Aug 12, 2021
- Intel Corporation
- Ziyin Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20210111088
- Publication date Apr 15, 2021
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING WAFER-LEVEL ACTIVE DIE AND EXTERNAL DI...
- Publication number 20210082826
- Publication date Mar 18, 2021
- Intel Corporation
- Vipul Vijay MEHTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH ATTACHMENT AND/OR STOP STRUCTURES
- Publication number 20210066162
- Publication date Mar 4, 2021
- Intel Corporation
- Sergio A. CHAN ARGUEDAS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DIE PACKAGE WITH WARPAGE MANAGEMENT AND PROCESS FOR F...
- Publication number 20210066152
- Publication date Mar 4, 2021
- Intel Corporation
- Ziyin LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRENCHES IN WAFER LEVEL PACKAGES FOR IMPROVEMENTS IN WARPAGE RELIAB...
- Publication number 20210035859
- Publication date Feb 4, 2021
- Intel Corporation
- Vipul MEHTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROTRUDING SN SUBSTRATE FEATURES FOR EPOXY FLOW CONTROL
- Publication number 20210020531
- Publication date Jan 21, 2021
- Intel Corporation
- Edvin CETEGEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO-ELECTRONIC PACKAGE WITH BARRIER STRUCTURE
- Publication number 20200006169
- Publication date Jan 2, 2020
- Intel Corporation
- William WARREN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICRO-ELECTRONIC PACKAGE WITH SUBSTRATE PROTRUSION TO FACILITATE DI...
- Publication number 20190304808
- Publication date Oct 3, 2019
- Intel Corporation
- Ziyin LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING WAFER-LEVEL ACTIVE DIE AND EXTERNAL DI...
- Publication number 20190279938
- Publication date Sep 12, 2019
- Intel Corporation
- Vipul Vijay MEHTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE PACKAGE
- Publication number 20190103361
- Publication date Apr 4, 2019
- Intel Corporation
- Digvijay A. Raorane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Package, and a Method for Forming a Semiconductor Pac...
- Publication number 20190006293
- Publication date Jan 3, 2019
- Intel Corporation
- John J Beatty
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC PACKAGE ASSEMBLY WITH COMPACT DIE PLACEMENT
- Publication number 20180190560
- Publication date Jul 5, 2018
- Intel Corporation
- Eric J. Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES AND CONFIGURATIONS FOR SURFACE TREATMENT OF AN INTEGRATE...
- Publication number 20140061902
- Publication date Mar 6, 2014
- Suriyakala Ramalingam
- H01 - BASIC ELECTRIC ELEMENTS

Vipul V. Mehta

Person

Patents Grantslast 30 patents

Hydrophobic feature to control adhesive flow

Protruding SN substrate features for epoxy flow control

Barrier structures for underfill containment

Package with underfill containment barrier

Micro-electronic package with substrate protrusion to facilitate di...

High thermal conductivity, high modulus structure within a mold mat...

Trenches in wafer level packages for improvements in warpage reliab...

Semiconductor die package with warpage management and process for f...

Package with underfill containment barrier

Semiconductor package having wafer-level active die and external di...

Micro-electronic package with substrate protrusion to facilitate di...

Package with underfill containment barrier

Semiconductor package having wafer-level active die and external di...

Electronic device package

Electronic package assembly with compact die placement

Semiconductor package, and a method for forming a semiconductor pac...

Techniques and configurations for surface treatment of an integrate...

Patents Applicationslast 30 patents

HYDROPHOBIC FEATURE TO CONTROL ADHESIVE FLOW

PROTRUDING SN SUBSTRATE FEATURES FOR EPOXY FLOW CONTROL

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

BARRIER ENABLED CUF AND MOLD PROCESS FOR MULTI-CHIP PACKAGING

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

HYDROPHOBIC FEATURE TO CONTROL ADHESIVE FLOW

MICRO-ELECTRONIC PACKAGE WITH SUBSTRATE PROTRUSION TO FACILITATE DI...

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

HIGH THERMAL CONDUCTIVITY, HIGH MODULUS STRUCTURE WITHIN A MOLD MAT...

BARRIER STRUCTURES FOR UNDERFILL CONTAINMENT

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

SEMICONDUCTOR PACKAGE HAVING WAFER-LEVEL ACTIVE DIE AND EXTERNAL DI...

SEMICONDUCTOR PACKAGE WITH ATTACHMENT AND/OR STOP STRUCTURES

SEMICONDUCTOR DIE PACKAGE WITH WARPAGE MANAGEMENT AND PROCESS FOR F...

TRENCHES IN WAFER LEVEL PACKAGES FOR IMPROVEMENTS IN WARPAGE RELIAB...

PROTRUDING SN SUBSTRATE FEATURES FOR EPOXY FLOW CONTROL

MICRO-ELECTRONIC PACKAGE WITH BARRIER STRUCTURE

MICRO-ELECTRONIC PACKAGE WITH SUBSTRATE PROTRUSION TO FACILITATE DI...

SEMICONDUCTOR PACKAGE HAVING WAFER-LEVEL ACTIVE DIE AND EXTERNAL DI...

ELECTRONIC DEVICE PACKAGE

Semiconductor Package, and a Method for Forming a Semiconductor Pac...

ELECTRONIC PACKAGE ASSEMBLY WITH COMPACT DIE PLACEMENT

TECHNIQUES AND CONFIGURATIONS FOR SURFACE TREATMENT OF AN INTEGRATE...