Virinder S. Grewal

Person

Fishkill, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for patterning integrated circuit conductors
- Patent number 6,071,820
- Issue date Jun 6, 2000
- Siemens Aktiengesellschaft
- Virinder Grewal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etching high aspect contact holes in solid state devices
- Patent number 6,008,121
- Issue date Dec 28, 1999
- Siemens Aktiengesellschaft
- Chi-Hua Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low pressure and low power C1.sub.2 /HC1 process for sub-micron met...
- Patent number 5,976,986
- Issue date Nov 2, 1999
- International Business Machines Corp.
- Munir D. Naeem
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process for reducing circuit damage during PECVD in single wafer PE...
- Patent number 5,926,689
- Issue date Jul 20, 1999
- International Business Machines Corporation
- Donna Rizzone Cote
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Polycide etching with HCL and chlorine
- Patent number 5,874,363
- Issue date Feb 23, 1999
- Kabushiki Kaisha Toshiba
- Peter D. Hoh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of self-aligned overlapping bitline contacts with sacrifi...
- Patent number 5,723,381
- Issue date Mar 3, 1998
- Siemens Aktiengesellschaft
- Virinder Grewal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch chamber having three independently controlled electrodes
- Patent number 5,597,438
- Issue date Jan 28, 1997
- Siemens Aktiengesellschaft
- Virinder S. Grewal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma etching method
- Patent number 5,591,301
- Issue date Jan 7, 1997
- Siemens Aktiengesellschaft
- Virinder S. Grewal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polysilicon/polycide etch process for sub-micron gate stacks
- Patent number 5,529,197
- Issue date Jun 25, 1996
- Siemens Aktiengesellschaft
- Virinder S. Grewal
- H01 - BASIC ELECTRIC ELEMENTS

Virinder S. Grewal

Person

Patents Grantslast 30 patents

Method for patterning integrated circuit conductors

Etching high aspect contact holes in solid state devices

Low pressure and low power C1.sub.2 /HC1 process for sub-micron met...

Process for reducing circuit damage during PECVD in single wafer PE...

Polycide etching with HCL and chlorine

Formation of self-aligned overlapping bitline contacts with sacrifi...

Etch chamber having three independently controlled electrodes

Plasma etching method

Polysilicon/polycide etch process for sub-micron gate stacks