Vishnu Kalyanamahadevi Gopalan Jawarlal

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for low noise sub-sampling phase lock loop (PLL)...
- Patent number 11,996,854
- Issue date May 28, 2024
- Samsung Electronics Co., Ltd.
- Sushrant Monga
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system of dynamically controlling reset signal of IQ div...
- Patent number 11,909,407
- Issue date Feb 20, 2024
- Samsung Electronics Co., Ltd.
- Praveen Rathee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reset synchronizing circuit and glitchless clock buffer circuit for...
- Patent number 11,804,945
- Issue date Oct 31, 2023
- Samsung Electronics Co., Ltd.
- Juyun Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for in-phase and quadrature phase (IQ) generation
- Patent number 11,728,792
- Issue date Aug 15, 2023
- Samsung Electronics Co., Ltd.
- Vishnu Kalyanamahadevi Gopalan Jawarlal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for generating sub harmonic locked frequency divi...
- Patent number 11,601,116
- Issue date Mar 7, 2023
- Samsung Electronics Co., Ltd.
- Gunjan Mandal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated device having phase interpolator and input controller th...
- Patent number 11,469,746
- Issue date Oct 11, 2022
- Samsung Electronics Co., Ltd.
- Vishnu Kalyanamahadevi Gopalan Jawarlal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ring oscillator and method for controlling start-up of ring oscillator
- Patent number 10,917,076
- Issue date Feb 9, 2021
- Samsung Electronics Co., Ltd.
- Vishnu Kalyanamahadevi Gopalan Jawarlal
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR LOW NOISE SUB-SAMPLING PHASE LOCK LOOP (PLL)...
- Publication number 20240007112
- Publication date Jan 4, 2024
- Samsung Electronics Co., Ltd.
- SUSHRANT MONGA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RESET SYNCHRONIZING CIRCUIT AND GLITCHLESS CLOCK BUFFER CIRCUIT FOR...
- Publication number 20230421343
- Publication date Dec 28, 2023
- Samsung Electronics Co., Ltd.
- Juyun LEE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND SYSTEM OF DYNAMICALLY CONTROLLING RESET SIGNAL OF IQ DIV...
- Publication number 20230412176
- Publication date Dec 21, 2023
- Samsung Electronics Co., Ltd.
- Praveen RATHEE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RESET SYNCHRONIZING CIRCUIT AND GLITCHLESS CLOCK BUFFER CIRCUIT FOR...
- Publication number 20230138296
- Publication date May 4, 2023
- Samsung Electronics Co., Ltd.
- Juyun LEE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHOD FOR IN-PHASE AND QUADRATURE PHASE (IQ) GENERATION
- Publication number 20230117732
- Publication date Apr 20, 2023
- Samsung Electronics Co., Ltd.
- VISHNU KALYANAMAHADEVI GOPALAN JAWARLAL
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM AND METHOD FOR GENERATING SUBHARMONIC LOCKED FREQUENCY DIVIS...
- Publication number 20220247392
- Publication date Aug 4, 2022
- Samsung Electronics Co., Ltd.
- Gunjan MANDAL
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED DEVICE HAVING PHASE INTERPOLATOR AND INPUT CONTROLLER TH...
- Publication number 20220231676
- Publication date Jul 21, 2022
- Samsung Electronics Co., Ltd.
- Vishnu Kalyanamahadevi Gopalan Jawarlal
- H03 - BASIC ELECTRONIC CIRCUITRY

Vishnu Kalyanamahadevi Gopalan Jawarlal

Person

Patents Grantslast 30 patents

Method and system for low noise sub-sampling phase lock loop (PLL)...

Method and system of dynamically controlling reset signal of IQ div...

Reset synchronizing circuit and glitchless clock buffer circuit for...

Apparatus and method for in-phase and quadrature phase (IQ) generation

System and method for generating sub harmonic locked frequency divi...

Integrated device having phase interpolator and input controller th...

Ring oscillator and method for controlling start-up of ring oscillator

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR LOW NOISE SUB-SAMPLING PHASE LOCK LOOP (PLL)...

RESET SYNCHRONIZING CIRCUIT AND GLITCHLESS CLOCK BUFFER CIRCUIT FOR...

METHOD AND SYSTEM OF DYNAMICALLY CONTROLLING RESET SIGNAL OF IQ DIV...

RESET SYNCHRONIZING CIRCUIT AND GLITCHLESS CLOCK BUFFER CIRCUIT FOR...

APPARATUS AND METHOD FOR IN-PHASE AND QUADRATURE PHASE (IQ) GENERATION

SYSTEM AND METHOD FOR GENERATING SUBHARMONIC LOCKED FREQUENCY DIVIS...

INTEGRATED DEVICE HAVING PHASE INTERPOLATOR AND INPUT CONTROLLER TH...