Viswanathan Lakshmanan

Person

Thornton, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Waiver mechanism for physical verification of system designs
- Patent number 8,046,726
- Issue date Oct 25, 2011
- LSI Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified layer stack architecture
- Patent number 7,853,901
- Issue date Dec 14, 2010
- LSI Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
N cell height decoupling circuit
- Patent number 7,829,973
- Issue date Nov 9, 2010
- LSI Corporation
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for layout versus schematic validation of integra...
- Patent number 7,480,878
- Issue date Jan 20, 2009
- LSI Logic Corportion
- Alan Lee Holesovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of automating place and route corrections for an integrated...
- Patent number 7,302,654
- Issue date Nov 27, 2007
- LSI Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental dummy metal insertions
- Patent number 7,260,803
- Issue date Aug 21, 2007
- LSI Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of implementing an engineering change order in an integrated...
- Patent number 7,231,626
- Issue date Jun 12, 2007
- LSI Corporation
- Jason K. Hoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and computer program for verifying an incremental change to...
- Patent number 7,219,317
- Issue date May 15, 2007
- LSI Logic Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of early physical design validation and identification of te...
- Patent number 7,149,989
- Issue date Dec 12, 2006
- LSI Logic Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of partitioning an integrated circuit design for physical de...
- Patent number 7,107,559
- Issue date Sep 12, 2006
- LSI Logic Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Web based OLA memory generator
- Patent number 7,051,318
- Issue date May 23, 2006
- LSI Logic Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing engineering change orders
- Patent number 7,007,248
- Issue date Feb 28, 2006
- LSI Logic Corporation
- Richard Blinne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip design method for designing integrated circuit chips with embe...
- Patent number 6,775,811
- Issue date Aug 10, 2004
- LSI Logic Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to debug IKOS method
- Patent number 6,691,288
- Issue date Feb 10, 2004
- LSI Logic Corporation
- Nader Fakhry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verilog to vital translator
- Patent number 6,668,359
- Issue date Dec 23, 2003
- LSI Logic Corporation
- Nader Fakhry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to translate UDPs using gate primitives
- Patent number 6,658,630
- Issue date Dec 2, 2003
- LSI Logic Corporation
- Vance Threatt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating standard delay format files with conditional path delay...
- Patent number 6,453,451
- Issue date Sep 17, 2002
- LSI Logic Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
WAIVER MECHANISM FOR PHYSICAL VERIFICATION OF SYSTEM DESIGNS
- Publication number 20100070936
- Publication date Mar 18, 2010
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Unified Layer Stack Architecture
- Publication number 20090271755
- Publication date Oct 29, 2009
- LSI Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
N CELL HEIGHT DECOUPLING CIRCUIT
- Publication number 20090051006
- Publication date Feb 26, 2009
- LSI Corporation
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and computer program product for trimming the analysis of ph...
- Publication number 20070157140
- Publication date Jul 5, 2007
- Alan Lee Holesovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of implementing an engineering change order in an integrated...
- Publication number 20060136855
- Publication date Jun 22, 2006
- LSI Logic Corporation
- Jason K. Hoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of automating place and route corrections for an integrated...
- Publication number 20060095883
- Publication date May 4, 2006
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of automating place and route corrections for an integrated...
- Publication number 20060090144
- Publication date Apr 27, 2006
- LSI Logic Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of early physical design validation and identification of te...
- Publication number 20060064656
- Publication date Mar 23, 2006
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and computer program for verifying an incremental change to...
- Publication number 20050235234
- Publication date Oct 20, 2005
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of partitioning an integrated circuit design for physical de...
- Publication number 20050097488
- Publication date May 5, 2005
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Incremental dummy metal insertions
- Publication number 20050080607
- Publication date Apr 14, 2005
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for implementing engineering change orders
- Publication number 20040230920
- Publication date Nov 18, 2004
- Richard Blinne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chip design method for designing integrated circuit chips with embe...
- Publication number 20030221177
- Publication date Nov 27, 2003
- LSI Logic Corporation
- Viswanathan Lakshmanan
- G06 - COMPUTING CALCULATING COUNTING

Viswanathan Lakshmanan

Person

Patents Grantslast 30 patents

Waiver mechanism for physical verification of system designs

Unified layer stack architecture

N cell height decoupling circuit

Method and system for layout versus schematic validation of integra...

Method of automating place and route corrections for an integrated...

Incremental dummy metal insertions

Method of implementing an engineering change order in an integrated...

Method and computer program for verifying an incremental change to...

Method of early physical design validation and identification of te...

Method of partitioning an integrated circuit design for physical de...

Web based OLA memory generator

Method and apparatus for implementing engineering change orders

Chip design method for designing integrated circuit chips with embe...

Method to debug IKOS method

Verilog to vital translator

Method to translate UDPs using gate primitives

Generating standard delay format files with conditional path delay...

Patents Applicationslast 30 patents

WAIVER MECHANISM FOR PHYSICAL VERIFICATION OF SYSTEM DESIGNS

Unified Layer Stack Architecture

N CELL HEIGHT DECOUPLING CIRCUIT

Method and computer program product for trimming the analysis of ph...

Method of implementing an engineering change order in an integrated...

Method of automating place and route corrections for an integrated...

Method of automating place and route corrections for an integrated...

Method of early physical design validation and identification of te...

Method and computer program for verifying an incremental change to...

Method of partitioning an integrated circuit design for physical de...

Incremental dummy metal insertions

Method and apparatus for implementing engineering change orders

Chip design method for designing integrated circuit chips with embe...