Vivek Chickermane

Person

Ithaca, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
3D stacked die testing structure
- Patent number 12,055,586
- Issue date Aug 6, 2024
- Cadence Design Systems, Inc.
- Sagar Kumar
- G01 - MEASURING TESTING
Information Patent Grant
Test-point flop sharing with improved testability in a circuit design
- Patent number 11,947,887
- Issue date Apr 2, 2024
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC chip test engine
- Patent number 11,379,644
- Issue date Jul 5, 2022
- Cadence Design Systems, Inc.
- Rajesh Khurana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IP block scan chain construction
- Patent number 11,256,839
- Issue date Feb 22, 2022
- Cadence Design Systems, Inc.
- Vivek Chickermane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to improve testability using 2-dimensional exclusive or (XOR...
- Patent number 10,955,470
- Issue date Mar 23, 2021
- Cadence Design Systems, Inc.
- Brian Edward Foutz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compacting test patterns for IJTAG test
- Patent number 10,796,041
- Issue date Oct 6, 2020
- Cadence Design Systems, Inc.
- Rajesh Khurana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power shift with clock staggering
- Patent number 10,775,435
- Issue date Sep 15, 2020
- Cadence Design Systems, Inc.
- Christos Papameletis
- G01 - MEASURING TESTING
Information Patent Grant
Method for optimally connecting scan segments in two-dimensional co...
- Patent number 10,761,131
- Issue date Sep 1, 2020
- Cadence Design Systems, Inc.
- Christos Papameletis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test circuitry with annularly arranged compressor and decompressor...
- Patent number 10,747,922
- Issue date Aug 18, 2020
- Cadence Design Systems, Inc.
- Akhil Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Devices and methods for test point insertion coverage
- Patent number 10,740,515
- Issue date Aug 11, 2020
- Cadence Design Systems, Inc.
- Jagjot Kaur
- G01 - MEASURING TESTING
Information Patent Grant
2D compression-based low power ATPG
- Patent number 10,551,435
- Issue date Feb 4, 2020
- Cadence Design Systems, Inc.
- Nitin Parimi
- G01 - MEASURING TESTING
Information Patent Grant
Verification process for IJTAG based test pattern migration
- Patent number 10,528,689
- Issue date Jan 7, 2020
- Cadence Design Systems, Inc.
- Rajesh Khurana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power and scan resource reduction in integrated circuit designs hav...
- Patent number 10,417,363
- Issue date Sep 17, 2019
- Cadence Design Systems, Inc.
- Jagjot Kaur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SoC top-level XOR compactor design to efficiently test and diagnose...
- Patent number 10,331,506
- Issue date Jun 25, 2019
- Cadence Design Systems, Inc.
- Vivek Chickermane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing core wrappers in an integrated circuit
- Patent number 10,234,504
- Issue date Mar 19, 2019
- Cadence Design Systems, Inc.
- Subhasish Mukherjee
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for construction of a highly efficient and predic...
- Patent number 9,817,069
- Issue date Nov 14, 2017
- Cadence Design Systems, Inc.
- Steev Wilcox
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for improving efficiency of sequential test compr...
- Patent number 9,817,068
- Issue date Nov 14, 2017
- Cadence Design Systems, Inc.
- Vivek Chickermane
- G01 - MEASURING TESTING
Information Patent Grant
Reducing mask data volume with elastic compression
- Patent number 9,702,934
- Issue date Jul 11, 2017
- Cadence Design Systems, Inc.
- Dale Edward Meehl
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for improving efficiency of XOR-based test compre...
- Patent number 9,606,179
- Issue date Mar 28, 2017
- Cadence Design Systems, Inc.
- Paul Alexander Cunningham
- G01 - MEASURING TESTING
Information Patent Grant
Method for using XOR trees for physically efficient scan compressio...
- Patent number 9,513,335
- Issue date Dec 6, 2016
- Cadence Design Systems, Inc.
- Steev Wilcox
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for testing integrated circuit designs
- Patent number 9,501,590
- Issue date Nov 22, 2016
- Cadence Design Systems, Inc.
- Paul A. Cunningham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for dividing testable logic into a two-dimensional grid for...
- Patent number 9,470,755
- Issue date Oct 18, 2016
- Cadence Design Systems, Inc.
- Brian Edward Foutz
- G01 - MEASURING TESTING
Information Patent Grant
Elastic compression-optimizing tester bandwidth with compressed tes...
- Patent number 9,470,754
- Issue date Oct 18, 2016
- Cadence Design Systems, Inc.
- Vivek Chickermane
- G01 - MEASURING TESTING
Information Patent Grant
Method for using sequential decompression logic for VLSI test in a...
- Patent number 9,470,756
- Issue date Oct 18, 2016
- Cadence Design Systems, Inc.
- Steev Wilcox
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for testing integrated circuit designs
- Patent number 9,465,896
- Issue date Oct 11, 2016
- Cadence Design Systems, Inc.
- Paul A. Cunningham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for low-pin count testing of integrated circuits
- Patent number 8,904,256
- Issue date Dec 2, 2014
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for automated extraction of a design for test...
- Patent number 8,732,632
- Issue date May 20, 2014
- Cadence Design Systems, Inc.
- Brion Keller
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for low-pin count testing of integrated circuits
- Patent number 8,650,524
- Issue date Feb 11, 2014
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for analyzing test vectors to determine toggle co...
- Patent number 8,615,692
- Issue date Dec 24, 2013
- Cadence Design Systems, Inc.
- Rajesh Khurana
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus to use physical design information to detect I...
- Patent number 8,595,681
- Issue date Nov 26, 2013
- Cadence Design Systems, Inc.
- Senthil Arasu Thirunavukarasu
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS
- Publication number 20090326854
- Publication date Dec 31, 2009
- Cadence Design Systems, Inc.
- Krishna CHAKRAVADHANULA
- G01 - MEASURING TESTING
Information Patent Application
DISTRIBUTED TEST COMPRESSION FOR INTEGRATED CIRCUITS
- Publication number 20090119559
- Publication date May 7, 2009
- Cadence Design Systems, Inc.
- Brian Foutz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test generation for low power circuits
- Publication number 20080071513
- Publication date Mar 20, 2008
- Cadence Design Systems, Inc.
- Vivek Chickermane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and mechanism for implementing electronic designs having pow...
- Publication number 20070245285
- Publication date Oct 18, 2007
- Qi Wang
- G06 - COMPUTING CALCULATING COUNTING

Vivek Chickermane

Person

Patents Grantslast 30 patents

3D stacked die testing structure

Test-point flop sharing with improved testability in a circuit design

IC chip test engine

IP block scan chain construction

Method to improve testability using 2-dimensional exclusive or (XOR...

Compacting test patterns for IJTAG test

Low-power shift with clock staggering

Method for optimally connecting scan segments in two-dimensional co...

Test circuitry with annularly arranged compressor and decompressor...

Devices and methods for test point insertion coverage

2D compression-based low power ATPG

Verification process for IJTAG based test pattern migration

Power and scan resource reduction in integrated circuit designs hav...

SoC top-level XOR compactor design to efficiently test and diagnose...

Optimizing core wrappers in an integrated circuit

Method and system for construction of a highly efficient and predic...

Method and system for improving efficiency of sequential test compr...

Reducing mask data volume with elastic compression

Method and system for improving efficiency of XOR-based test compre...

Method for using XOR trees for physically efficient scan compressio...

Systems and methods for testing integrated circuit designs

Method for dividing testable logic into a two-dimensional grid for...

Elastic compression-optimizing tester bandwidth with compressed tes...

Method for using sequential decompression logic for VLSI test in a...

Systems and methods for testing integrated circuit designs

Method and apparatus for low-pin count testing of integrated circuits

Method and apparatus for automated extraction of a design for test...

Method and apparatus for low-pin count testing of integrated circuits

Method and system for analyzing test vectors to determine toggle co...

Method and apparatus to use physical design information to detect I...

Patents Applicationslast 30 patents

TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS

DISTRIBUTED TEST COMPRESSION FOR INTEGRATED CIRCUITS

Test generation for low power circuits

Method and mechanism for implementing electronic designs having pow...