Vivek Kumar Yadav

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Austin, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
System on a chip (SoC) having a low power mode of operation
- Patent number 12,306,652
- Issue date May 20, 2025
- NXP USA, INC.
- Vivek Kumar Yadav
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
FAULT INTERFACE ARCHITECTURE IN SAFETY-RELEVANT SYSTEMS
- Publication number 20250156261
- Publication date May 15, 2025
- NXP USA, Inc.
- Kumar Abhishek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM ON A CHIP (SOC) HAVING A LOW POWER MODE OF OPERATION
- Publication number 20250123648
- Publication date Apr 17, 2025
- NXP USA, Inc.
- Vivek Kumar Yadav
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-CHIP FAULT DETECTION DUE TO MALFUNCTIONS ON CHIP PINS
- Publication number 20240353479
- Publication date Oct 24, 2024
- NXP USA, Inc.
- Kumar Abhishek
- H03 - BASIC ELECTRONIC CIRCUITRY