Vivek Singhal

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for test time reduction using fractional data...
- Patent number 9,970,987
- Issue date May 15, 2018
- Texas Instruments Incorporated
- Sreenath Narayanan Potty
- G01 - MEASURING TESTING
Information Patent Grant
Area-optimized retention flop implementation
- Patent number 9,705,481
- Issue date Jul 11, 2017
- Texas Instruments Incorporated
- Sudesh Chandra Srivastava
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Frequency scaled segmented scan chain for integrated circuits
- Patent number 9,535,123
- Issue date Jan 3, 2017
- Texas Instruments Incorporated
- Rajesh Kumar Mittal
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for test time reduction using fractional data...
- Patent number 9,448,284
- Issue date Sep 20, 2016
- Texas Instruments Incorporated
- Sreenath Narayanan Potty
- G01 - MEASURING TESTING
Information Patent Grant
Phase shifted coarse/fine clock dithering responsive to controller...
- Patent number 9,419,630
- Issue date Aug 16, 2016
- Texas Instruments Incorporated
- Sreenath Narayanan Potty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for reducing gate leakage of low threshold tra...
- Patent number 9,319,045
- Issue date Apr 19, 2016
- Texas Instruments Incorporated
- Sudesh Chandra Srivastava
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
IC delaying flip-flop output partial clock cycle for equalizing cur...
- Patent number 9,053,273
- Issue date Jun 9, 2015
- Texas Instruments Incorporated
- Sumanth Reddy Poddutur
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interference mitigation output frequency determined by division fac...
- Patent number 8,981,821
- Issue date Mar 17, 2015
- Texas Instruments Incorporated
- Sreenath Narayanan Potty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and method for spur supression in a multiple radio SoC
- Patent number 8,750,805
- Issue date Jun 10, 2014
- Texas Instruments Incorporated
- Vivek Singhal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interference mitigation in mixed signal integrated circuits (ICs)
- Patent number 8,698,539
- Issue date Apr 15, 2014
- Texas Instruments Incorporated
- Jasbir Singh Nayyar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for aligning input signals
- Patent number 8,058,902
- Issue date Nov 15, 2011
- Texas Instruments Incorporated
- Sahil Khurana
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AREA-OPTIMIZED RETENTION FLOP IMPLEMENTATION
- Publication number 20170194949
- Publication date Jul 6, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Sudesh Chandra Srivastava
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and Apparatus for Test Time Reduction Using Fractional Data...
- Publication number 20160356849
- Publication date Dec 8, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Sreenath Narayanan Potty
- G01 - MEASURING TESTING
Information Patent Application
Frequency Scaled Segmented Scan Chain for Integrated Circuits
- Publication number 20160266202
- Publication date Sep 15, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Rajesh Kumar Mittal
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND APPARATUS TO SUPPRESS DIGITAL NOISE SPURS USING MULTI-ST...
- Publication number 20160191066
- Publication date Jun 30, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Sreenath Narayanan Potty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR TEST TIME REDUCTION USING FRACTIONAL DATA...
- Publication number 20150323596
- Publication date Nov 12, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Sreenath Narayanan Potty
- G01 - MEASURING TESTING
Information Patent Application
CIRCUITS AND METHODS FOR SIGNAL INTERFERENCE MITIGATION
- Publication number 20140197875
- Publication date Jul 17, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Sreenath Narayanan Potty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS TO SUPPRESS POWER SUPPLY NOISE HARMONICS IN...
- Publication number 20140021993
- Publication date Jan 23, 2014
- TEXAS INSTRUMENTS INCORPORATED
- SUMANTH REDDY PODDUTUR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHOD FOR SPUR SUPRESSION IN A MULTIPLE RADIO SoC
- Publication number 20120154010
- Publication date Jun 21, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Vivek Singhal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
FLIP-FLOP ARCHITECTURE FOR MITIGATING HOLD CLOSURE
- Publication number 20120062298
- Publication date Mar 15, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Sumanth Reddy PODDUTUR
- H03 - BASIC ELECTRONIC CIRCUITRY

Vivek Singhal

Person

Patents Grantslast 30 patents

Method and apparatus for test time reduction using fractional data...

Area-optimized retention flop implementation

Frequency scaled segmented scan chain for integrated circuits

Method and apparatus for test time reduction using fractional data...

Phase shifted coarse/fine clock dithering responsive to controller...

Method and apparatus for reducing gate leakage of low threshold tra...

IC delaying flip-flop output partial clock cycle for equalizing cur...

Interference mitigation output frequency determined by division fac...

Systems and method for spur supression in a multiple radio SoC

Interference mitigation in mixed signal integrated circuits (ICs)

Circuit for aligning input signals

Patents Applicationslast 30 patents

AREA-OPTIMIZED RETENTION FLOP IMPLEMENTATION

Method and Apparatus for Test Time Reduction Using Fractional Data...

Frequency Scaled Segmented Scan Chain for Integrated Circuits

METHOD AND APPARATUS TO SUPPRESS DIGITAL NOISE SPURS USING MULTI-ST...

METHOD AND APPARATUS FOR TEST TIME REDUCTION USING FRACTIONAL DATA...

CIRCUITS AND METHODS FOR SIGNAL INTERFERENCE MITIGATION

APPARATUSES AND METHODS TO SUPPRESS POWER SUPPLY NOISE HARMONICS IN...

SYSTEMS AND METHOD FOR SPUR SUPRESSION IN A MULTIPLE RADIO SoC

FLIP-FLOP ARCHITECTURE FOR MITIGATING HOLD CLOSURE