Vivekanandan Venugopal

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hybrid pulse/two-stage data latch
- Patent number 11,870,442
- Issue date Jan 9, 2024
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power down detection for non-destructive isolation signal generation
- Patent number 11,579,642
- Issue date Feb 14, 2023
- Apple Inc.
- Vivekanandan Venugopal
- G05 - CONTROLLING REGULATING
Information Patent Grant
Flip-flop circuit with glitch protection
- Patent number 11,496,120
- Issue date Nov 8, 2022
- Apple Inc.
- Qi Ye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low voltage clock swing tolerant sequential circuits for dynamic po...
- Patent number 11,424,734
- Issue date Aug 23, 2022
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid pulse/two-stage data latch
- Patent number 11,418,173
- Issue date Aug 16, 2022
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient retention flop utilizing different voltage domain
- Patent number 11,418,174
- Issue date Aug 16, 2022
- Apple Inc.
- Greg M. Hess
- G11 - INFORMATION STORAGE
Information Patent Grant
Semi dynamic flop and single stage pulse flop with shadow latch and...
- Patent number 11,303,268
- Issue date Apr 12, 2022
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
No-enable setup clock gater based on pulse
- Patent number 11,258,446
- Issue date Feb 22, 2022
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Level-shifting transparent window sense amplifier
- Patent number 11,164,611
- Issue date Nov 2, 2021
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power flip-flop with balanced clock-to-Q delay
- Patent number 11,139,803
- Issue date Oct 5, 2021
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power down detection for non-destructive isolation signal generation
- Patent number 11,132,010
- Issue date Sep 28, 2021
- Apple Inc.
- Vivekanandan Venugopal
- G01 - MEASURING TESTING
Information Patent Grant
Low voltage clock swing tolerant sequential circuits for dynamic po...
- Patent number 11,018,653
- Issue date May 25, 2021
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Efficient retention flop utilizing different voltage domain
- Patent number 11,005,459
- Issue date May 11, 2021
- Apple Inc.
- Greg M. Hess
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulsed level shifter circuitry
- Patent number 10,903,824
- Issue date Jan 26, 2021
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Level shifter with isolation on both input and output domains with...
- Patent number 10,838,483
- Issue date Nov 17, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid pulse/master-slave data latch
- Patent number 10,742,201
- Issue date Aug 11, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Level-shifting transparent window sense amplifier
- Patent number 10,734,040
- Issue date Aug 4, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid power switch
- Patent number 10,732,693
- Issue date Aug 4, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulsed level shifter circuitry
- Patent number 10,581,412
- Issue date Mar 3, 2020
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flop circuit with integrated clock gating circuit
- Patent number 10,491,197
- Issue date Nov 26, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power clock gating circuit
- Patent number 10,461,747
- Issue date Oct 29, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Master-slave clock generation circuit
- Patent number 10,270,433
- Issue date Apr 23, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid power switch
- Patent number 10,261,563
- Issue date Apr 16, 2019
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Level shifting circuit with data resolution and grounded input nodes
- Patent number 10,187,061
- Issue date Jan 22, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Hybrid Pulse/Two-Stage Data Latch
- Publication number 20220345117
- Publication date Oct 27, 2022
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flip-Flop Circuit with Glitch Protection
- Publication number 20220231673
- Publication date Jul 21, 2022
- Apple Inc.
- Qi Ye
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Power Down Detection for Non-Destructive Isolation Signal Generation
- Publication number 20220043469
- Publication date Feb 10, 2022
- Apple Inc.
- Vivekanandan Venugopal
- G01 - MEASURING TESTING
Information Patent Application
Low Voltage Clock Swing Tolerant Sequential Circuits for Dynamic Po...
- Publication number 20210344329
- Publication date Nov 4, 2021
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NO-ENABLE SETUP CLOCK GATER BASED ON PULSE
- Publication number 20210344344
- Publication date Nov 4, 2021
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Retention Flop Utilizing Different Voltage Domain
- Publication number 20210250019
- Publication date Aug 12, 2021
- Apple Inc.
- Greg M. Hess
- G11 - INFORMATION STORAGE
Information Patent Application
Semi Dynamic Flop and Single Stage Pulse Flop with Shadow Latch and...
- Publication number 20210167759
- Publication date Jun 3, 2021
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Hybrid Pulse/Two-Stage Data Latch
- Publication number 20200373915
- Publication date Nov 26, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PULSED LEVEL SHIFTER CIRCUITRY
- Publication number 20200313660
- Publication date Oct 1, 2020
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMI DYNAMIC FLOP AND SINGLE STAGE PULSE FLOP WITH SHADOW LATCH AND...
- Publication number 20200106424
- Publication date Apr 2, 2020
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HYBRID PULSE/MASTER-SLAVE DATA LATCH
- Publication number 20200106425
- Publication date Apr 2, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEVEL SHIFTER WITH ISOLATION ON BOTH INPUT AND OUTPUT DOMAINS WITH...
- Publication number 20200103957
- Publication date Apr 2, 2020
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID POWER SWITCH
- Publication number 20190235602
- Publication date Aug 1, 2019
- Apple Inc.
- Vivekanandan Venugopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flop Circuit with Integrated Clock Gating Circuit
- Publication number 20190089337
- Publication date Mar 21, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low Power Clock Gating Circuit
- Publication number 20190089354
- Publication date Mar 21, 2019
- Apple Inc.
- Vivekanandan Venugopal
- H03 - BASIC ELECTRONIC CIRCUITRY

Vivekanandan Venugopal

Person

Patents Grantslast 30 patents

Hybrid pulse/two-stage data latch

Power down detection for non-destructive isolation signal generation

Flip-flop circuit with glitch protection

Low voltage clock swing tolerant sequential circuits for dynamic po...

Hybrid pulse/two-stage data latch

Efficient retention flop utilizing different voltage domain

Semi dynamic flop and single stage pulse flop with shadow latch and...

No-enable setup clock gater based on pulse

Level-shifting transparent window sense amplifier

Low power flip-flop with balanced clock-to-Q delay

Power down detection for non-destructive isolation signal generation

Low voltage clock swing tolerant sequential circuits for dynamic po...

Efficient retention flop utilizing different voltage domain

Pulsed level shifter circuitry

Level shifter with isolation on both input and output domains with...

Hybrid pulse/master-slave data latch

Level-shifting transparent window sense amplifier

Hybrid power switch

Pulsed level shifter circuitry

Flop circuit with integrated clock gating circuit

Low power clock gating circuit

Master-slave clock generation circuit

Hybrid power switch

Level shifting circuit with data resolution and grounded input nodes

Patents Applicationslast 30 patents

Hybrid Pulse/Two-Stage Data Latch

Flip-Flop Circuit with Glitch Protection

Power Down Detection for Non-Destructive Isolation Signal Generation

Low Voltage Clock Swing Tolerant Sequential Circuits for Dynamic Po...

NO-ENABLE SETUP CLOCK GATER BASED ON PULSE

Efficient Retention Flop Utilizing Different Voltage Domain

Semi Dynamic Flop and Single Stage Pulse Flop with Shadow Latch and...

Hybrid Pulse/Two-Stage Data Latch

PULSED LEVEL SHIFTER CIRCUITRY

SEMI DYNAMIC FLOP AND SINGLE STAGE PULSE FLOP WITH SHADOW LATCH AND...

HYBRID PULSE/MASTER-SLAVE DATA LATCH

LEVEL SHIFTER WITH ISOLATION ON BOTH INPUT AND OUTPUT DOMAINS WITH...

HYBRID POWER SWITCH

Flop Circuit with Integrated Clock Gating Circuit

Low Power Clock Gating Circuit