Vivien Renauld

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Pontcharra, FR

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Patents Grantslast 30 patents

Information Patent Grant
Method for reducing the trap density in a semiconductor wafer
- Patent number 7,601,606
- Issue date Oct 13, 2009
- S.O.I. Tec Silicon on Insulator Technologies
- Francois Brunier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for applying a high temperature heat treatment to a semicond...
- Patent number 7,585,793
- Issue date Sep 8, 2009
- S.O.I. Tec Silicon on Insulator Technologies
- Christophe Maleville
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for high-temperature annealing a multilayer wafer
- Patent number 7,544,058
- Issue date Jun 9, 2009
- S.O.I. Tec Silicon on Insulator Technologies
- Christophe Maleville
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR HIGH-TEMPERATURE ANNEALING A MULTILAYER WAFER
- Publication number 20070298363
- Publication date Dec 27, 2007
- Christophe Malleville
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for applying a high temperature heat treatment to a semicond...
- Publication number 20070026692
- Publication date Feb 1, 2007
- Christophe Maleville
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing the trap density in a semiconductor wafer
- Publication number 20070020886
- Publication date Jan 25, 2007
- Francois Brunier
- H01 - BASIC ELECTRIC ELEMENTS