W. Story Leavesley, III

Person

Longmont, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Generating a module interface for partial reconfiguration design flows
- Patent number 8,332,788
- Issue date Dec 11, 2012
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification of logic core implementation
- Patent number 8,286,113
- Issue date Oct 9, 2012
- Xilinx, Inc.
- Brendan K. Bridgford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a module interface for partial reconfiguration design flows
- Patent number 7,941,777
- Issue date May 10, 2011
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design independent correlation data storage for use with physical d...
- Patent number 7,810,055
- Issue date Oct 5, 2010
- Xilinx, Inc.
- Brian J. Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Versatile bus interface macro for dynamically reconfigurable designs
- Patent number 7,619,442
- Issue date Nov 17, 2009
- Xilinx, Inc.
- Jeffrey M. Mason
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for circuit design closure using partitions
- Patent number 7,620,927
- Issue date Nov 17, 2009
- Xilinx, Inc.
- Emil S. Ochotta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Plug-in component-based dependency management for partitions within...
- Patent number 7,590,951
- Issue date Sep 15, 2009
- Xilinx, Inc.
- William R. Bell, II
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partition-based incremental implementation flow for use with a prog...
- Patent number 7,490,312
- Issue date Feb 10, 2009
- Xilinx, Inc.
- Emil S. Ochotta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Versatile bus interface macro for dynamically reconfigurable designs
- Patent number 7,478,357
- Issue date Jan 13, 2009
- Xilinx, Inc.
- Jeffrey M. Mason
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing a pre-implemented circuit des...
- Patent number 7,392,498
- Issue date Jun 24, 2008
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING

W. Story Leavesley, III

Person

Patents Grantslast 30 patents

Generating a module interface for partial reconfiguration design flows

Verification of logic core implementation

Generating a module interface for partial reconfiguration design flows

Design independent correlation data storage for use with physical d...

Versatile bus interface macro for dynamically reconfigurable designs

Method and apparatus for circuit design closure using partitions

Plug-in component-based dependency management for partitions within...

Partition-based incremental implementation flow for use with a prog...

Versatile bus interface macro for dynamically reconfigurable designs

Method and apparatus for implementing a pre-implemented circuit des...