Walid HAFEZ

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-aligned gate endcap (SAGE) architecture having gate contacts
- Patent number 12,199,101
- Issue date Jan 14, 2025
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar I/O and logic semiconductor devices having different wor...
- Patent number 12,191,207
- Issue date Jan 7, 2025
- Intel Corporation
- Roman W. Olac-Vaw
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration of Si-based transistors with non-Si technologies by sem...
- Patent number 12,148,757
- Issue date Nov 19, 2024
- Intel Corporation
- Nidhi Nidhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High voltage three-dimensional devices having dielectric liners
- Patent number 12,136,628
- Issue date Nov 5, 2024
- Intel Corporation
- Walid M. Hafez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated fuse in self-aligned gate endcap for FinFET architecture...
- Patent number 12,108,595
- Issue date Oct 1, 2024
- Intel Corporation
- Sumit Ashtekar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned front-end charge trap flash memory cell and capacitor...
- Patent number 12,089,411
- Issue date Sep 10, 2024
- Intel Corporation
- Tanuj Trivedi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide for group III-nitride devices and methods of fabrication
- Patent number 12,080,763
- Issue date Sep 3, 2024
- Intel Corporation
- Sansaptak Dasgupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High voltage extended-drain MOS (EDMOS) nanowire transistors
- Patent number 12,040,395
- Issue date Jul 16, 2024
- Intel Corporation
- Nidhi Nidhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-N transistor arrangements for reducing nonlinearity of off-stat...
- Patent number 12,027,613
- Issue date Jul 2, 2024
- Intel Corporation
- Nidhi Nidhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD diode solution for nanoribbon architectures
- Patent number 11,996,403
- Issue date May 28, 2024
- Intel Corporation
- Nidhi Nidhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual threshold voltage (VT) channel devices and their methods of fa...
- Patent number 11,967,615
- Issue date Apr 23, 2024
- Intel Corporation
- Hsu-Yu Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architecture having gate contacts
- Patent number 11,935,892
- Issue date Mar 19, 2024
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Superlattice FINFET with tunable drive current capability
- Patent number 11,881,511
- Issue date Jan 23, 2024
- Intel Corporation
- Nidhi Nidhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High voltage three-dimensional devices having dielectric liners
- Patent number 11,881,486
- Issue date Jan 23, 2024
- Intel Corporation
- Walid M. Hafez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architecture having gate or contact...
- Patent number 11,876,121
- Issue date Jan 16, 2024
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having dual nanoribbo...
- Patent number 11,862,703
- Issue date Jan 2, 2024
- Intel Corporation
- Tanuj Trivedi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-N transistors with contacts of modified widths
- Patent number 11,848,362
- Issue date Dec 19, 2023
- Intel Corporation
- Rahul Ramaswamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Variable pitch and stack height for high performance interconnects
- Patent number 11,824,002
- Issue date Nov 21, 2023
- Intel Corporation
- En-Shao Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar I/O and logic semiconductor devices having different wor...
- Patent number 11,823,954
- Issue date Nov 21, 2023
- Intel Corporation
- Roman W. Olac-Vaw
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device terminal interconnect structures
- Patent number 11,791,257
- Issue date Oct 17, 2023
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single gated 3D nanowire inverter for high density thick gate SOC a...
- Patent number 11,791,380
- Issue date Oct 17, 2023
- Intel Corporation
- Rahul Ramaswamy
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Dielectric and isolation lower fin material for fin-based electronics
- Patent number 11,764,260
- Issue date Sep 19, 2023
- Tahoe Research, LTD.
- Walid M. Hafez
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
E-D mode 2DEG FET with gate spacer to locally tune VT and improve b...
- Patent number 11,757,027
- Issue date Sep 12, 2023
- Intel Corporation
- Rahul Ramaswamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal fuse and self-aligned gate edge (SAGE) architecture having a...
- Patent number 11,715,737
- Issue date Aug 1, 2023
- Intel Corporation
- Rohan K. Bambery
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Charge-induced threshold voltage tuning in III-N transistors
- Patent number 11,715,790
- Issue date Aug 1, 2023
- Intel Corporation
- Nidhi Nidhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate endcap (SAGE) architecture having local interconn...
- Patent number 11,705,453
- Issue date Jul 18, 2023
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of integrating multiple gate dielectric transistors on a tr...
- Patent number 11,695,008
- Issue date Jul 4, 2023
- Intel Corporation
- Curtis Tsai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual self-aligned gate endcap (SAGE) architectures
- Patent number 11,688,792
- Issue date Jun 27, 2023
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor gate structure with hybrid stacks of dielectric material
- Patent number 11,688,788
- Issue date Jun 27, 2023
- Intel Corporation
- Johann C. Rode
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-N transistors with local stressors for threshold voltage control
- Patent number 11,670,709
- Issue date Jun 6, 2023
- Intel Corporation
- Sansaptak Dasgupta
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS
- Publication number 20250031446
- Publication date Jan 23, 2025
- Intel Corporation
- Walid M. HAFEZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE CONTACTS
- Publication number 20250022881
- Publication date Jan 16, 2025
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED BACKBONE FOR FORKSHEET TRANSISTORS
- Publication number 20240213250
- Publication date Jun 27, 2024
- Intel Corporation
- Shao Ming KOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHEMICAL MECHANICAL POLISHING OF CARBON HARD MASK
- Publication number 20240194732
- Publication date Jun 13, 2024
- Intel Corporation
- Matthew J. Prince
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE CONTACTS
- Publication number 20240145477
- Publication date May 2, 2024
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS
- Publication number 20240113128
- Publication date Apr 4, 2024
- Intel Corporation
- Walid M. HAFEZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DUAL NANORIBBO...
- Publication number 20240088253
- Publication date Mar 14, 2024
- Intel Corporation
- Tanuj TRIVEDI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR I/O AND LOGIC SEMICONDUCTOR DEVICES HAVING DIFFERENT WOR...
- Publication number 20240038592
- Publication date Feb 1, 2024
- Intel Corporation
- ROMAN W. OLAC-VAW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE GATED 3D NANOWIRE INVERTER FOR HIGH DENSITY THICK GATE SOC A...
- Publication number 20230420501
- Publication date Dec 28, 2023
- Intel Corporation
- Rahul RAMASWAMY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE PERFORMANCE TUNING BY DEEP TRENCH VIA (DVB) PROXIMITY EFFECT...
- Publication number 20230317594
- Publication date Oct 5, 2023
- Tao CHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE PROCESSING OF FINS IN FIN BASED TRANSISTOR DEVICES
- Publication number 20230307449
- Publication date Sep 28, 2023
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...
- Publication number 20230299081
- Publication date Sep 21, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TR...
- Publication number 20230299087
- Publication date Sep 21, 2023
- Intel Corporation
- Curtis TSAI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...
- Publication number 20230299165
- Publication date Sep 21, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS
- Publication number 20230207569
- Publication date Jun 29, 2023
- Intel Corporation
- Walid M. HAFEZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNOLOGIES FOR THERMOELECTRIC-ENHANCED COOLING
- Publication number 20230207421
- Publication date Jun 29, 2023
- Intel Corporation
- Han Wui Then
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GROUP III-NITRIDE SEMICONDUCTOR ARRAY WITH HETEROGENEOUS ELECTRODES...
- Publication number 20230102318
- Publication date Mar 30, 2023
- Intel Corporation
- Rahul Ramaswamy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GALLIUM NITRIDE (GAN) LAYER TRANSFER FOR INTEGRATED CIRCUIT TECHNOLOGY
- Publication number 20230090106
- Publication date Mar 23, 2023
- Intel Corporation
- Han Wui THEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE VIA BAR SELF-ALIGNED TO GATE END
- Publication number 20220399445
- Publication date Dec 15, 2022
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DUAL NANORIBBO...
- Publication number 20220359697
- Publication date Nov 10, 2022
- Intel Corporation
- Tanuj TRIVEDI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE OR CONTACT...
- Publication number 20220359705
- Publication date Nov 10, 2022
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE CONTACTS
- Publication number 20220352165
- Publication date Nov 3, 2022
- INTEL CORPORATION
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICIDE FOR GROUP III-NITRIDE DEVICES AND METHODS OF FABRICATION
- Publication number 20220293738
- Publication date Sep 15, 2022
- Intel Corporation
- Sansaptak DASGUPTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR I/O AND LOGIC SEMICONDUCTOR DEVICES HAVING DIFFERENT WOR...
- Publication number 20220238383
- Publication date Jul 28, 2022
- Intel Corporation
- ROMAN W. OLAC-VAW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL FUSE AND SELF-ALIGNED GATE EDGE (SAGE) ARCHITECTURE HAVING A...
- Publication number 20220173105
- Publication date Jun 2, 2022
- Intel Corporation
- Rohan K. BAMBERY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR SEMICONDUCTOR DEVICE HAVING OMEGA-FIN WITH DOPED SUB-FIN...
- Publication number 20220130962
- Publication date Apr 28, 2022
- Intel Corporation
- GOPINATH BHIMARASETTI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS
- Publication number 20220130871
- Publication date Apr 28, 2022
- Intel Corporation
- Walid M. HAFEZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE TERMINAL INTERCONNECT STRUCTURES
- Publication number 20220122911
- Publication date Apr 21, 2022
- Intel Corporation
- Sairam Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC AND ISOLATION LOWER FIN MATERIAL FOR FIN-BASED ELECTRONICS
- Publication number 20220102488
- Publication date Mar 31, 2022
- Intel Corporation
- Walid M. HAFEZ
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADJACENT GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NON-M...
- Publication number 20220093588
- Publication date Mar 24, 2022
- Intel Corporation
- Sairam SUBRAMANIAN
- H01 - BASIC ELECTRIC ELEMENTS

Walid HAFEZ

Person

Patents Grantslast 30 patents

Self-aligned gate endcap (SAGE) architecture having gate contacts

Non-planar I/O and logic semiconductor devices having different wor...

Integration of Si-based transistors with non-Si technologies by sem...

High voltage three-dimensional devices having dielectric liners

Integrated fuse in self-aligned gate endcap for FinFET architecture...

Self-aligned front-end charge trap flash memory cell and capacitor...

Silicide for group III-nitride devices and methods of fabrication

High voltage extended-drain MOS (EDMOS) nanowire transistors

III-N transistor arrangements for reducing nonlinearity of off-stat...

ESD diode solution for nanoribbon architectures

Dual threshold voltage (VT) channel devices and their methods of fa...

Self-aligned gate endcap (SAGE) architecture having gate contacts

Superlattice FINFET with tunable drive current capability

High voltage three-dimensional devices having dielectric liners

Self-aligned gate endcap (SAGE) architecture having gate or contact...

Gate-all-around integrated circuit structures having dual nanoribbo...

III-N transistors with contacts of modified widths

Variable pitch and stack height for high performance interconnects

Non-planar I/O and logic semiconductor devices having different wor...

Device terminal interconnect structures

Single gated 3D nanowire inverter for high density thick gate SOC a...

Dielectric and isolation lower fin material for fin-based electronics

E-D mode 2DEG FET with gate spacer to locally tune VT and improve b...

Metal fuse and self-aligned gate edge (SAGE) architecture having a...

Charge-induced threshold voltage tuning in III-N transistors

Self-aligned gate endcap (SAGE) architecture having local interconn...

Methods of integrating multiple gate dielectric transistors on a tr...

Dual self-aligned gate endcap (SAGE) architectures

Transistor gate structure with hybrid stacks of dielectric material

III-N transistors with local stressors for threshold voltage control

Patents Applicationslast 30 patents

HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE CONTACTS

SELF-ALIGNED BACKBONE FOR FORKSHEET TRANSISTORS

CHEMICAL MECHANICAL POLISHING OF CARBON HARD MASK

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE CONTACTS

HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DUAL NANORIBBO...

NON-PLANAR I/O AND LOGIC SEMICONDUCTOR DEVICES HAVING DIFFERENT WOR...

SINGLE GATED 3D NANOWIRE INVERTER FOR HIGH DENSITY THICK GATE SOC A...

DEVICE PERFORMANCE TUNING BY DEEP TRENCH VIA (DVB) PROXIMITY EFFECT...

BACKSIDE PROCESSING OF FINS IN FIN BASED TRANSISTOR DEVICES

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...

METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TR...

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...

HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS

TECHNOLOGIES FOR THERMOELECTRIC-ENHANCED COOLING

GROUP III-NITRIDE SEMICONDUCTOR ARRAY WITH HETEROGENEOUS ELECTRODES...

GALLIUM NITRIDE (GAN) LAYER TRANSFER FOR INTEGRATED CIRCUIT TECHNOLOGY

CONDUCTIVE VIA BAR SELF-ALIGNED TO GATE END

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DUAL NANORIBBO...

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE OR CONTACT...

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURE HAVING GATE CONTACTS

SILICIDE FOR GROUP III-NITRIDE DEVICES AND METHODS OF FABRICATION

NON-PLANAR I/O AND LOGIC SEMICONDUCTOR DEVICES HAVING DIFFERENT WOR...

METAL FUSE AND SELF-ALIGNED GATE EDGE (SAGE) ARCHITECTURE HAVING A...

NON-PLANAR SEMICONDUCTOR DEVICE HAVING OMEGA-FIN WITH DOPED SUB-FIN...

HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS

DEVICE TERMINAL INTERCONNECT STRUCTURES

DIELECTRIC AND ISOLATION LOWER FIN MATERIAL FOR FIN-BASED ELECTRONICS

ADJACENT GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING NON-M...