Warren E. Maule

Person

Cedar Park, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Efficient and selective sparing of bits in memory systems
- Patent number 11,698,842
- Issue date Jul 11, 2023
- International Business Machines Corporation
- Stephen Glancy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient and selective sparing of bits in memory systems
- Patent number 11,645,171
- Issue date May 9, 2023
- International Business Machines Corporation
- Stephen Glancy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to reduce bandwidth overhead of CRC protection...
- Patent number 11,593,196
- Issue date Feb 28, 2023
- International Business Machines Corporation
- Kevin M. Mcilvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address/command chip controlled data chip address sequencing for a...
- Patent number 11,587,600
- Issue date Feb 21, 2023
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid memory mirroring using storage class memory
- Patent number 11,586,360
- Issue date Feb 21, 2023
- International Business Machines Corporation
- Peter J. Heyrman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant voltage regulator for memory devices
- Patent number 11,264,077
- Issue date Mar 1, 2022
- International Business Machines Corporation
- Brian J. Connolly
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to reduce bandwidth overhead of CRC protection...
- Patent number 11,200,112
- Issue date Dec 14, 2021
- International Business Machines Corporation
- Kevin M. Mcilvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient and selective sparing of bits in memory systems
- Patent number 11,182,262
- Issue date Nov 23, 2021
- International Business Machines Corporation
- Stephen Glancy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using dual channel memory as single channel memory with spares
- Patent number 11,037,619
- Issue date Jun 15, 2021
- International Business Machines Corporation
- Kyu-Hyoun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Tracking address ranges for computer memory errors
- Patent number 11,017,875
- Issue date May 25, 2021
- International Business Machines Corporation
- John S. Dodson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing error correction in computer memory
- Patent number 10,971,246
- Issue date Apr 6, 2021
- International Business Machines Corporation
- John S. Dodson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant voltage regulator for memory devices
- Patent number 10,937,485
- Issue date Mar 2, 2021
- International Business Machines Corporation
- Brian J. Connolly
- G11 - INFORMATION STORAGE
Information Patent Grant
Common high and low random bit error correction logic
- Patent number 10,901,839
- Issue date Jan 26, 2021
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Common high and low random bit error correction logic
- Patent number 10,824,504
- Issue date Nov 3, 2020
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host controlled data chip address sequencing for a distributed memo...
- Patent number 10,747,442
- Issue date Aug 18, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient and selective sparing of bits in memory systems
- Patent number 10,671,497
- Issue date Jun 2, 2020
- International Business Machines Corporation
- Stephen Glancy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Autonomous dram scrub and error counting
- Patent number 10,628,248
- Issue date Apr 21, 2020
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory mirror invocation upon detecting a correctable error
- Patent number 10,613,951
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Marc A. Gollub
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction potency improvement via added burst beats in a dra...
- Patent number 10,606,692
- Issue date Mar 31, 2020
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using dual channel memory as single channel memory with command add...
- Patent number 10,606,713
- Issue date Mar 31, 2020
- International Business Machines Corporation
- Kyu-Hyoun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Auto-disabling DRAM error checking on threshold
- Patent number 10,592,332
- Issue date Mar 17, 2020
- International Business Machines Corporation
- Edgar R. Cordero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using dual channel memory as single channel memory with spares
- Patent number 10,546,628
- Issue date Jan 28, 2020
- International Business Machines Corporation
- Kyu-Hyoun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional stacked memory optimizations for latency and power
- Patent number 10,534,545
- Issue date Jan 14, 2020
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-dimensional stacked memory access optimization
- Patent number 10,528,288
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing DRAM row hammer avoidance
- Patent number 10,497,409
- Issue date Dec 3, 2019
- International Business Machines Corporation
- Charles A. Kilmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant voltage regulator for memory devices
- Patent number 10,468,088
- Issue date Nov 5, 2019
- International Business Machines Corporation
- Brian J. Connolly
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing DRAM row hammer avoidance
- Patent number 10,453,503
- Issue date Oct 22, 2019
- International Business Machines Corporation
- Charles A. Kilmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address/command chip controlled data chip address sequencing for a...
- Patent number 10,395,698
- Issue date Aug 27, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power management in multi-channel 3D stacked DRAM
- Patent number 10,353,455
- Issue date Jul 16, 2019
- International Business Machines Corporation
- Kevin M. Mcilvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing entries in a mark table of computer memory errors
- Patent number 10,353,669
- Issue date Jul 16, 2019
- International Business Machines Corporation
- John S. Dodson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HYBRID MEMORY MIRRORING USING STORAGE CLASS MEMORY
- Publication number 20220365685
- Publication date Nov 17, 2022
- International Business Machines Corporation
- Peter J. Heyrman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS TO REDUCE BANDWIDTH OVERHEAD OF CRC PROTECTION...
- Publication number 20220091927
- Publication date Mar 24, 2022
- International Business Machines Corporation
- Kevin M. Mcilvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT AND SELECTIVE SPARING OF BITS IN MEMORY SYSTEMS
- Publication number 20220027243
- Publication date Jan 27, 2022
- International Business Machines Corporation
- Stephen Glancy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANT VOLTAGE REGULATOR FOR MEMORY DEVICES
- Publication number 20210134346
- Publication date May 6, 2021
- International Business Machines Corporation
- Brian J. Connolly
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENT AND SELECTIVE SPARING OF BITS IN MEMORY SYSTEMS
- Publication number 20200226040
- Publication date Jul 16, 2020
- International Business Machines Corporation
- Stephen Glancy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC
- Publication number 20200097359
- Publication date Mar 26, 2020
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING DUAL CHANNEL MEMORY AS SINGLE CHANNEL MEMORY WITH SPARES
- Publication number 20200075079
- Publication date Mar 5, 2020
- International Business Machines Corporation
- Kyu-Hyoun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
REDUNDANT VOLTAGE REGULATOR FOR MEMORY DEVICES
- Publication number 20200013449
- Publication date Jan 9, 2020
- International Business Machines Corporation
- Brian J. Connolly
- G11 - INFORMATION STORAGE
Information Patent Application
COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC
- Publication number 20190317856
- Publication date Oct 17, 2019
- International Business Machines Corporation
- James A. O'Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address/Command Chip Controlled Data Chip Address Sequencing for a...
- Publication number 20190252010
- Publication date Aug 15, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING ERROR CORRECTION IN COMPUTER MEMORY
- Publication number 20190244676
- Publication date Aug 8, 2019
- International Business Machines Corporation
- JOHN S. DODSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient and Selective Sparing of Bits in Memory Systems
- Publication number 20190227886
- Publication date Jul 25, 2019
- International Business Machines Corporation
- Stephen Glancy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACKING ADDRESS RANGES FOR COMPUTER MEMORY ERRORS
- Publication number 20190221280
- Publication date Jul 18, 2019
- International Business Machines Corporation
- JOHN S. DODSON
- G11 - INFORMATION STORAGE
Information Patent Application
USING DUAL CHANNEL MEMORY AS SINGLE CHANNEL MEMORY WITH SPARES
- Publication number 20190206477
- Publication date Jul 4, 2019
- International Business Machines Corporation
- Kyu-Hyoun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
USING DUAL CHANNEL MEMORY AS SINGLE CHANNEL MEMORY WITH COMMAND ADD...
- Publication number 20190205225
- Publication date Jul 4, 2019
- International Business Machines Corporation
- Kyu-Hyoun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANT VOLTAGE REGULATOR FOR MEMORY DEVICES
- Publication number 20190189182
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Brian J. Connolly
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR CORRECTION POTENCY IMPROVEMENT VIA ADDED BURST BEATS IN A DRA...
- Publication number 20190188074
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Paul W. Coteus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE-DIMENSIONAL STACKED MEMORY OPTIMIZATIONS FOR LATENCY AND POWER
- Publication number 20190187915
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE-DIMENSIONAL STACKED MEMORY ACCESS OPTIMIZATION
- Publication number 20190187930
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Diyanesh B. Chinnakkonda Vidyapoornachary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Host Controlled Data Chip Address Sequencing for a Distributed Memo...
- Publication number 20190163362
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address/Command Chip Controlled Data Chip Address Sequencing for A...
- Publication number 20190163383
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MIRROR INVOCATION UPON DETECTING A CORRECTABLE ERROR
- Publication number 20190079840
- Publication date Mar 14, 2019
- International Business Machines Corporation
- Marc A. Gollub
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGEMENT IN MULTI-CHANNEL 3D STACKED DRAM
- Publication number 20190033949
- Publication date Jan 31, 2019
- International Business Machines Corporation
- Kevin M. Mcilvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGEMENT IN MULTI-CHANNEL 3D STACKED DRAM
- Publication number 20190033952
- Publication date Jan 31, 2019
- International Business Machines Corporation
- Kevin M. Mcilvain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTO-DISABLING DRAM ERROR CHECKING ON THRESHOLD
- Publication number 20180246781
- Publication date Aug 30, 2018
- International Business Machines Corporation
- Edgar R. Cordero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA BUFFER SPARE ARCHITECTURES FOR DUAL CHANNEL SERIAL INTERFACE M...
- Publication number 20180150369
- Publication date May 31, 2018
- International Business Machines Corporation
- Kyu-Hyoun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT CALIBRATION OF MEMORY DEVICES
- Publication number 20180075887
- Publication date Mar 15, 2018
- International Business Machines Corporation
- John S. Bialas
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIRMING MEMORY MARKS INDICATING AN ERROR IN COMPUTER MEMORY
- Publication number 20180067806
- Publication date Mar 8, 2018
- International Business Machines Corporation
- JOHN S. DODSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACKING ADDRESS RANGES FOR COMPUTER MEMORY ERRORS
- Publication number 20180068741
- Publication date Mar 8, 2018
- International Business Machines Corporation
- JOHN S. DODSON
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING ENTRIES IN A MARK TABLE OF COMPUTER MEMORY ERRORS
- Publication number 20180067719
- Publication date Mar 8, 2018
- International Business Machines Corporation
- JOHN S. DODSON
- G06 - COMPUTING CALCULATING COUNTING

Warren E. Maule

Person

Patents Grantslast 30 patents

Efficient and selective sparing of bits in memory systems

Efficient and selective sparing of bits in memory systems

Method and apparatus to reduce bandwidth overhead of CRC protection...

Address/command chip controlled data chip address sequencing for a...

Hybrid memory mirroring using storage class memory

Redundant voltage regulator for memory devices

Method and apparatus to reduce bandwidth overhead of CRC protection...

Efficient and selective sparing of bits in memory systems

Using dual channel memory as single channel memory with spares

Tracking address ranges for computer memory errors

Performing error correction in computer memory

Redundant voltage regulator for memory devices

Common high and low random bit error correction logic

Common high and low random bit error correction logic

Host controlled data chip address sequencing for a distributed memo...

Efficient and selective sparing of bits in memory systems

Autonomous dram scrub and error counting

Memory mirror invocation upon detecting a correctable error

Error correction potency improvement via added burst beats in a dra...

Using dual channel memory as single channel memory with command add...

Auto-disabling DRAM error checking on threshold

Using dual channel memory as single channel memory with spares

Three-dimensional stacked memory optimizations for latency and power

Three-dimensional stacked memory access optimization

Implementing DRAM row hammer avoidance

Redundant voltage regulator for memory devices

Implementing DRAM row hammer avoidance

Address/command chip controlled data chip address sequencing for a...

Power management in multi-channel 3D stacked DRAM

Managing entries in a mark table of computer memory errors

Patents Applicationslast 30 patents

HYBRID MEMORY MIRRORING USING STORAGE CLASS MEMORY

METHOD AND APPARATUS TO REDUCE BANDWIDTH OVERHEAD OF CRC PROTECTION...

EFFICIENT AND SELECTIVE SPARING OF BITS IN MEMORY SYSTEMS

REDUNDANT VOLTAGE REGULATOR FOR MEMORY DEVICES

EFFICIENT AND SELECTIVE SPARING OF BITS IN MEMORY SYSTEMS

COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC

USING DUAL CHANNEL MEMORY AS SINGLE CHANNEL MEMORY WITH SPARES

REDUNDANT VOLTAGE REGULATOR FOR MEMORY DEVICES

COMMON HIGH AND LOW RANDOM BIT ERROR CORRECTION LOGIC

Address/Command Chip Controlled Data Chip Address Sequencing for a...

PERFORMING ERROR CORRECTION IN COMPUTER MEMORY

Efficient and Selective Sparing of Bits in Memory Systems

TRACKING ADDRESS RANGES FOR COMPUTER MEMORY ERRORS

USING DUAL CHANNEL MEMORY AS SINGLE CHANNEL MEMORY WITH SPARES

USING DUAL CHANNEL MEMORY AS SINGLE CHANNEL MEMORY WITH COMMAND ADD...

REDUNDANT VOLTAGE REGULATOR FOR MEMORY DEVICES

ERROR CORRECTION POTENCY IMPROVEMENT VIA ADDED BURST BEATS IN A DRA...

THREE-DIMENSIONAL STACKED MEMORY OPTIMIZATIONS FOR LATENCY AND POWER

THREE-DIMENSIONAL STACKED MEMORY ACCESS OPTIMIZATION

Host Controlled Data Chip Address Sequencing for a Distributed Memo...

Address/Command Chip Controlled Data Chip Address Sequencing for A...

MEMORY MIRROR INVOCATION UPON DETECTING A CORRECTABLE ERROR

POWER MANAGEMENT IN MULTI-CHANNEL 3D STACKED DRAM

POWER MANAGEMENT IN MULTI-CHANNEL 3D STACKED DRAM

AUTO-DISABLING DRAM ERROR CHECKING ON THRESHOLD

DATA BUFFER SPARE ARCHITECTURES FOR DUAL CHANNEL SERIAL INTERFACE M...

EFFICIENT CALIBRATION OF MEMORY DEVICES

CONFIRMING MEMORY MARKS INDICATING AN ERROR IN COMPUTER MEMORY

TRACKING ADDRESS RANGES FOR COMPUTER MEMORY ERRORS

MANAGING ENTRIES IN A MARK TABLE OF COMPUTER MEMORY ERRORS