Wataru Tsukada

Person

Tokyo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Memory module on which regular chips and error correction chips are...
- Patent number 8,510,629
- Issue date Aug 13, 2013
- Elpida Memory, Inc.
- Wataru Tsukada
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory module and layout method therefor
- Patent number 8,462,535
- Issue date Jun 11, 2013
- Elpida Memory, Inc.
- Shiro Harashima
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module and layout method therefor
- Patent number 8,243,488
- Issue date Aug 14, 2012
- Elpida Memory, Inc.
- Shiro Harashima
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory module and layout method therefor
- Patent number 8,054,664
- Issue date Nov 8, 2011
- Elpida Memory, Inc.
- Shiro Harashima
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor module, wiring board, and wiring method
- Patent number 8,054,643
- Issue date Nov 8, 2011
- Elpida Memory, Inc.
- Wataru Tsukada
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR MODULE HAVING MODULE SUBSTRATE AND PLURAL SEMICONDUCT...
- Publication number 20130010514
- Publication date Jan 10, 2013
- ELPIDA MEMORY, INC.
- Wataru TSUKADA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE AND LAYOUT METHOD THEREFOR
- Publication number 20120281348
- Publication date Nov 8, 2012
- Elpida Memory, Inc.
- Shiro Harashima
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE AND LAYOUT METHOD THEREFOR
- Publication number 20120026772
- Publication date Feb 2, 2012
- Elpida Memory, Inc.
- Shiro Harashima
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE ON WHICH REGULAR CHIPS AND ERROR CORRECTION CHIPS ARE...
- Publication number 20110093764
- Publication date Apr 21, 2011
- Elpida Memory, Inc.
- Wataru TSUKADA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE AND LAYOUT METHOD THEREFOR
- Publication number 20100157645
- Publication date Jun 24, 2010
- Elpida Memory, Inc.
- Shiro Harashima
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MODULE
- Publication number 20090236758
- Publication date Sep 24, 2009
- Elpida Memory, Inc.
- Wataru Tsukada
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Semiconductor module, wiring board , and wiring method
- Publication number 20090196009
- Publication date Aug 6, 2009
- Elpida Memory,Inc.
- Wataru TSUKADA
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Wataru Tsukada

Person

Patents Grantslast 30 patents

Memory module on which regular chips and error correction chips are...

Memory module and layout method therefor

Memory module and layout method therefor

Memory module and layout method therefor

Semiconductor module, wiring board, and wiring method

Patents Applicationslast 30 patents

SEMICONDUCTOR MODULE HAVING MODULE SUBSTRATE AND PLURAL SEMICONDUCT...

MEMORY MODULE AND LAYOUT METHOD THEREFOR

MEMORY MODULE AND LAYOUT METHOD THEREFOR

MEMORY MODULE ON WHICH REGULAR CHIPS AND ERROR CORRECTION CHIPS ARE...

MEMORY MODULE AND LAYOUT METHOD THEREFOR

SEMICONDUCTOR MODULE

Semiconductor module, wiring board , and wiring method