WAYNE BAO

Person

Shanghai, CN

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device with three or four-terminal-FinFET
- Patent number 9,570,468
- Issue date Feb 14, 2017
- Semiconductor Manufacturing International (Shanghai) Corporation
- Wayne Bao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and manufacturing method thereof
- Patent number 9,379,240
- Issue date Jun 28, 2016
- Semiconductor Manufacturing International (Shanghai) Corporation
- Wayne Bao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming fin FET structure with dual-stress spacers
- Patent number 9,312,386
- Issue date Apr 12, 2016
- Semiconductor Manufacturing International Corp
- Wayne Bao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication method for semiconductor device with three or four-term...
- Patent number 9,287,182
- Issue date Mar 15, 2016
- Semiconductor Manufacturing International (Shanghai) Corporation
- Wayne Bao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fin FET structure with dual-stress spacers and method for forming t...
- Patent number 9,099,558
- Issue date Aug 4, 2015
- Semiconductor Manufacturing International Corp
- Wayne Bao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and manufacturing method thereof
- Patent number 8,871,622
- Issue date Oct 28, 2014
- Semicondoctor Manufacturing International (Shanghai) Corporation
- Wayne Bao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal silicide layer, NMOS transistor, and fabrication method
- Patent number 8,865,593
- Issue date Oct 21, 2014
- Semiconductor Manufacturing International Corp
- Haibo Xiao
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE WITH THREE OR FOUR-TERMINAL-FINFET
- Publication number 20160155758
- Publication date Jun 2, 2016
- Semiconductor Manufacturing International (Shanghai) Corporation
- WAYNE BAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING FIN FET STRUCTURE WITH DUAL-STRESS SPACERS
- Publication number 20150303304
- Publication date Oct 22, 2015
- Semiconductor Manufacturing International Corp.
- Wayne BAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20150021673
- Publication date Jan 22, 2015
- Semiconductor Manufacturing International (Shanghai) Corporation
- Wayne BAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND FABRICATION METHOD
- Publication number 20140167166
- Publication date Jun 19, 2014
- Semiconductor Manufacturing International (Shanghai) Corporation
- WAYNE BAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number 20140077277
- Publication date Mar 20, 2014
- Semiconductor Manufacturing International (Beijing) Corporation
- Wayne BAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL SILICIDE LAYER, NMOS TRANSISTOR, AND FABRICATION METHOD
- Publication number 20130341687
- Publication date Dec 26, 2013
- HAIBO XIAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN FET STRUCTURE WITH DUAL-STRESS SPACERS AND METHOD FOR FORMING T...
- Publication number 20130168748
- Publication date Jul 4, 2013
- Wayne BAO
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Semiconductor device with three or four-terminal-FinFET

Semiconductor device and manufacturing method thereof

Method for forming fin FET structure with dual-stress spacers

Fabrication method for semiconductor device with three or four-term...

Fin FET structure with dual-stress spacers and method for forming t...

Semiconductor device and manufacturing method thereof

Metal silicide layer, NMOS transistor, and fabrication method

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE WITH THREE OR FOUR-TERMINAL-FINFET

METHOD FOR FORMING FIN FET STRUCTURE WITH DUAL-STRESS SPACERS

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR DEVICE AND FABRICATION METHOD

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

METAL SILICIDE LAYER, NMOS TRANSISTOR, AND FABRICATION METHOD

FIN FET STRUCTURE WITH DUAL-STRESS SPACERS AND METHOD FOR FORMING T...