Wayne E. Werner

Person

Coopersburg, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Secure random number generator
- Patent number 8,566,377
- Issue date Oct 22, 2013
- Agere Systems LLC
- Edward B. Harris
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimization of circuits having repeatable circuit instances
- Patent number 8,516,408
- Issue date Aug 20, 2013
- LSI Corporation
- Richard Bruce Dell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-reliability memory
- Patent number 8,468,419
- Issue date Jun 18, 2013
- LSI Corporation
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit self-monitored burn-in
- Patent number 8,405,412
- Issue date Mar 26, 2013
- LSI Corporation
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with error correction based on automatic logic inversion
- Patent number 8,365,044
- Issue date Jan 29, 2013
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with phase distribution circuit for controlling relat...
- Patent number 8,284,622
- Issue date Oct 9, 2012
- LSI Corporation
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with error correction capability and efficient partia...
- Patent number 8,156,402
- Issue date Apr 10, 2012
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Systematic error correction for multi-level flash memory
- Patent number 8,139,412
- Issue date Mar 20, 2012
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Tracking circuit for reducing faults in a memory
- Patent number 8,125,842
- Issue date Feb 28, 2012
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Process and temperature tolerant non-volatile memory
- Patent number 8,059,472
- Issue date Nov 15, 2011
- Agere Systems Inc.
- Dennis Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for testing a memory device
- Patent number 8,023,348
- Issue date Sep 20, 2011
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having a memory with process-voltage-temperature...
- Patent number 7,948,819
- Issue date May 24, 2011
- Agere Systems Inc.
- Mathew R. Henry
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for increasing yield in a memory device
- Patent number 7,940,594
- Issue date May 10, 2011
- Agere Systems Inc.
- Richard Bruce Dell
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with reduced buffer current during power-down mode
- Patent number 7,933,155
- Issue date Apr 26, 2011
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with error correction capability and preemptive parti...
- Patent number 7,930,615
- Issue date Apr 19, 2011
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with redundancy
- Patent number 7,898,887
- Issue date Mar 1, 2011
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Accessing memory cells in a memory circuit
- Patent number 7,872,929
- Issue date Jan 18, 2011
- LSI Corporation
- Richard Bruce Dell
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit having reduced power consumption
- Patent number 7,848,172
- Issue date Dec 7, 2010
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line driver circuit with reduced leakage
- Patent number 7,826,301
- Issue date Nov 2, 2010
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Process and temperature tolerant non-volatile memory
- Patent number 7,755,948
- Issue date Jul 13, 2010
- Agere Systems Inc.
- Dennis Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple-level memory with analog read
- Patent number 7,746,692
- Issue date Jun 29, 2010
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic random access memory with low-power refresh
- Patent number 7,742,355
- Issue date Jun 22, 2010
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced leakage driver circuit and memory device employing same
- Patent number 7,633,830
- Issue date Dec 15, 2009
- Agere Systems Inc.
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for idle cycle refresh request in DRAM
- Patent number 7,613,061
- Issue date Nov 3, 2009
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell for content-addressable memory
- Patent number 7,558,095
- Issue date Jul 7, 2009
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-port memory
- Patent number 7,551,512
- Issue date Jun 23, 2009
- Agere Systems Inc.
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Grant
Accelerated single-ended sensing for a memory circuit
- Patent number 7,433,254
- Issue date Oct 7, 2008
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Accelerated searching for content-addressable memory
- Patent number 7,391,633
- Issue date Jun 24, 2008
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Layout techniques for memory circuitry
- Patent number 7,324,364
- Issue date Jan 29, 2008
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Grant
Decoding techniques for read-only memory
- Patent number 7,301,828
- Issue date Nov 27, 2007
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Memory Device with Phase Distribution Circuit for Controlling Relat...
- Publication number 20120075946
- Publication date Mar 29, 2012
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
Process and Temperature Tolerant Non-Volatile Memory
- Publication number 20110222357
- Publication date Sep 15, 2011
- Agerre Systems, Inc.
- Dennis Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Cell Using Leakage Current Storage Mechanism
- Publication number 20110157964
- Publication date Jun 30, 2011
- Richard J. McPartland
- G11 - INFORMATION STORAGE
Information Patent Application
High-Reliability Memory
- Publication number 20110055660
- Publication date Mar 3, 2011
- Dennis E. Dudeck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure Random Number Generator
- Publication number 20110022648
- Publication date Jan 27, 2011
- Edward B. Harris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Optimization of Circuits Having Repeatable Circuit Instances
- Publication number 20100301926
- Publication date Dec 2, 2010
- Richard Bruce Dell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated Circuit Self-Monitored Burn-In
- Publication number 20100271064
- Publication date Oct 28, 2010
- Ross A. Kohler
- G01 - MEASURING TESTING
Information Patent Application
Accessing Memory Cells in a Memory Circuit
- Publication number 20100271891
- Publication date Oct 28, 2010
- Richard Bruce Dell
- G11 - INFORMATION STORAGE
Information Patent Application
Tracking Circuit for Reducing Faults in a Memory
- Publication number 20100246293
- Publication date Sep 30, 2010
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Increasing Yield in a Memory Device
- Publication number 20100238751
- Publication date Sep 23, 2010
- Agere Systems Inc.
- Richard Bruce Dell
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMATIC ERROR CORRECTION FOR MULTI-LEVEL FLASH MEMORY
- Publication number 20100229035
- Publication date Sep 9, 2010
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device with Reduced Buffer Current During Power-Down Mode
- Publication number 20100220534
- Publication date Sep 2, 2010
- Agere Systems Inc.
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Testing a Memory Device
- Publication number 20100182859
- Publication date Jul 22, 2010
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Application
Word Line Driver Circuit with Reduced Leakage
- Publication number 20100165778
- Publication date Jul 1, 2010
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Sense Amplifier with Redundancy
- Publication number 20100157707
- Publication date Jun 24, 2010
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device with Error Correction Capability and Efficient Partia...
- Publication number 20100131825
- Publication date May 27, 2010
- Ross A. Kohler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Circuit Having Reduced Power Consumption
- Publication number 20100128549
- Publication date May 27, 2010
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Process and Temperature Tolerant Non-Volatile Memory
- Publication number 20100046291
- Publication date Feb 25, 2010
- Agere Systems, Inc.
- Dennis Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Multiple-Level Memory with Analog Read
- Publication number 20090196098
- Publication date Aug 6, 2009
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Application
Dynamic Random Access Memory With Low-Power Refresh
- Publication number 20090161459
- Publication date Jun 25, 2009
- Agere Systems Inc.
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Application
Reduced Leakage Driver Circuit and Memory Device Employing Same
- Publication number 20090141580
- Publication date Jun 4, 2009
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
Method and Apparatus for Idle Cycle Refresh Request in Dram
- Publication number 20090141575
- Publication date Jun 4, 2009
- Ross A. Kohler
- G11 - INFORMATION STORAGE
Information Patent Application
Dual-Port Memory
- Publication number 20090034356
- Publication date Feb 5, 2009
- Donald Albert Evans
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device with Error Correction Capability and Preemptive Parti...
- Publication number 20080301526
- Publication date Dec 4, 2008
- Ross A. Kohler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Cell for Content-Addressable Memory
- Publication number 20080273361
- Publication date Nov 6, 2008
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Device with Error Correction Based on Automatic Logic Inversion
- Publication number 20080263385
- Publication date Oct 23, 2008
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT HAVING A MEMORY WITH PROCESS-VOLTAGE-TEMPERATURE...
- Publication number 20080117702
- Publication date May 22, 2008
- Agere Systems Inc.
- Matthew R. Henry
- G11 - INFORMATION STORAGE
Information Patent Application
Accelerated Single-Ended Sensing for a Memory Circuit
- Publication number 20080025103
- Publication date Jan 31, 2008
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Accelerated Searching for Content-Addressable Memory
- Publication number 20080025119
- Publication date Jan 31, 2008
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE
Information Patent Application
Layout techniques for read-only memory and the like
- Publication number 20070201257
- Publication date Aug 30, 2007
- Dennis E. Dudeck
- G11 - INFORMATION STORAGE

Wayne E. Werner

Person

Patents Grantslast 30 patents

Secure random number generator

Optimization of circuits having repeatable circuit instances

High-reliability memory

Integrated circuit self-monitored burn-in

Memory device with error correction based on automatic logic inversion

Memory device with phase distribution circuit for controlling relat...

Memory device with error correction capability and efficient partia...

Systematic error correction for multi-level flash memory

Tracking circuit for reducing faults in a memory

Process and temperature tolerant non-volatile memory

Method and apparatus for testing a memory device

Integrated circuit having a memory with process-voltage-temperature...

Method and apparatus for increasing yield in a memory device

Memory device with reduced buffer current during power-down mode

Memory device with error correction capability and preemptive parti...

Sense amplifier with redundancy

Accessing memory cells in a memory circuit

Memory circuit having reduced power consumption

Word line driver circuit with reduced leakage

Process and temperature tolerant non-volatile memory

Multiple-level memory with analog read

Dynamic random access memory with low-power refresh

Reduced leakage driver circuit and memory device employing same

Method and apparatus for idle cycle refresh request in DRAM

Memory cell for content-addressable memory

Dual-port memory

Accelerated single-ended sensing for a memory circuit

Accelerated searching for content-addressable memory

Layout techniques for memory circuitry

Decoding techniques for read-only memory

Patents Applicationslast 30 patents

Memory Device with Phase Distribution Circuit for Controlling Relat...

Process and Temperature Tolerant Non-Volatile Memory

Memory Cell Using Leakage Current Storage Mechanism

High-Reliability Memory

Secure Random Number Generator

Optimization of Circuits Having Repeatable Circuit Instances

Integrated Circuit Self-Monitored Burn-In

Accessing Memory Cells in a Memory Circuit

Tracking Circuit for Reducing Faults in a Memory

Method and Apparatus for Increasing Yield in a Memory Device

SYSTEMATIC ERROR CORRECTION FOR MULTI-LEVEL FLASH MEMORY

Memory Device with Reduced Buffer Current During Power-Down Mode

Method and Apparatus for Testing a Memory Device

Word Line Driver Circuit with Reduced Leakage

Sense Amplifier with Redundancy

Memory Device with Error Correction Capability and Efficient Partia...

Memory Circuit Having Reduced Power Consumption

Process and Temperature Tolerant Non-Volatile Memory

Multiple-Level Memory with Analog Read

Dynamic Random Access Memory With Low-Power Refresh

Reduced Leakage Driver Circuit and Memory Device Employing Same

Method and Apparatus for Idle Cycle Refresh Request in Dram

Dual-Port Memory

Memory Device with Error Correction Capability and Preemptive Parti...

Memory Cell for Content-Addressable Memory

Memory Device with Error Correction Based on Automatic Logic Inversion

INTEGRATED CIRCUIT HAVING A MEMORY WITH PROCESS-VOLTAGE-TEMPERATURE...

Accelerated Single-Ended Sensing for a Memory Circuit

Accelerated Searching for Content-Addressable Memory

Layout techniques for read-only memory and the like