Weidan Li

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Power/ground layout for chips
- Patent number 8,946,890
- Issue date Feb 3, 2015
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Laterally diffused metal oxide semiconductor (LDMOS) device with ov...
- Patent number 8,921,938
- Issue date Dec 30, 2014
- Marvell International Ltd.
- Xin Yi Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
On-chip automatic process variation, supply voltage variation, and...
- Patent number 7,321,254
- Issue date Jan 22, 2008
- LSI Logic Corporation
- Weidan Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of optimizing critical path delay in an integrated circuit d...
- Patent number 7,181,712
- Issue date Feb 20, 2007
- LSI Logic Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized buffering for JTAG boundary scan nets
- Patent number 7,000,163
- Issue date Feb 14, 2006
- LSI Logic Corporation
- Juergen Dirks
- G01 - MEASURING TESTING
Information Patent Grant
Low via resistance system
- Patent number 6,893,962
- Issue date May 17, 2005
- LSI Logic Corporation
- Prabhakar P. Tripathi
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Decoupling capacitance estimation and insertion flow for ASIC designs
- Patent number 6,807,656
- Issue date Oct 19, 2004
- LSI Logic Corporation
- Lihui Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit structure having low dielectric constant materia...
- Patent number 6,794,756
- Issue date Sep 21, 2004
- LSI Logic Corporation
- Weidan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low dielectric constant silicon oxide-based dielectric layer for in...
- Patent number 6,756,674
- Issue date Jun 29, 2004
- LSI Logic Corporation
- Wilbur G. Catabay
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Low leakage PMOS on-chip decoupling capacitor cells compatible with...
- Patent number 6,608,365
- Issue date Aug 19, 2003
- LSI Logic Corporation
- Weidan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low via resistance system
- Patent number 6,569,751
- Issue date May 27, 2003
- LSI Logic Corporation
- Prabhakar P. Tripathi
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of forming integrated circuit structure having low dielectri...
- Patent number 6,423,628
- Issue date Jul 23, 2002
- LSI Logic Corporation
- Weidan Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for CMP removal of excess trench or via filler metal which...
- Patent number 6,391,768
- Issue date May 21, 2002
- LSI Logic Corporation
- Dawn M. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tungsten local interconnect for silicon integrated circuit structur...
- Patent number 6,329,720
- Issue date Dec 11, 2001
- LSI Logic Corporation
- Weidan Li
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
POWER/GROUND LAYOUT FOR CHIPS
- Publication number 20150155202
- Publication date Jun 4, 2015
- Marvell World Trade Ltd.
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER/GROUND LAYOUT FOR CHIPS
- Publication number 20120098127
- Publication date Apr 26, 2012
- Sehat Sutardja
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
On-chip automatic process variation, supply voltage variation, and...
- Publication number 20060119420
- Publication date Jun 8, 2006
- Weidan Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method of optimizing critical path delay in an integrated circuit d...
- Publication number 20060090145
- Publication date Apr 27, 2006
- LSI Logic Corporation
- Benjamin Mbouombouo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DECOUPLING CAPACITANCE ESTIMATION AND INSERTION FLOW FOR ASIC DESIGNS
- Publication number 20040199882
- Publication date Oct 7, 2004
- Lihui Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low via resistance system
- Publication number 20030203622
- Publication date Oct 30, 2003
- LSI Logic Corporation
- Prabhakar P. Tripathi
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Integrated circuit structure having low dielectric constant materia...
- Publication number 20020135040
- Publication date Sep 26, 2002
- Weidan Li
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Power/ground layout for chips

Laterally diffused metal oxide semiconductor (LDMOS) device with ov...

On-chip automatic process variation, supply voltage variation, and...

Method of optimizing critical path delay in an integrated circuit d...

Optimized buffering for JTAG boundary scan nets

Low via resistance system

Decoupling capacitance estimation and insertion flow for ASIC designs

Integrated circuit structure having low dielectric constant materia...

Low dielectric constant silicon oxide-based dielectric layer for in...

Low leakage PMOS on-chip decoupling capacitor cells compatible with...

Low via resistance system

Method of forming integrated circuit structure having low dielectri...

Process for CMP removal of excess trench or via filler metal which...

Tungsten local interconnect for silicon integrated circuit structur...

Patents Applicationslast 30 patents

POWER/GROUND LAYOUT FOR CHIPS

POWER/GROUND LAYOUT FOR CHIPS

On-chip automatic process variation, supply voltage variation, and...

Method of optimizing critical path delay in an integrated circuit d...

DECOUPLING CAPACITANCE ESTIMATION AND INSERTION FLOW FOR ASIC DESIGNS

Low via resistance system

Integrated circuit structure having low dielectric constant materia...