Weirong Jiang

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Content addressable memory decomposition
- Patent number 9,899,088
- Issue date Feb 20, 2018
- Xilinx, Inc.
- Weirong Jiang
- G11 - INFORMATION STORAGE
Information Patent Grant
High throughput packet state processing
- Patent number 9,756,154
- Issue date Sep 5, 2017
- Xilinx, Inc.
- Weirong Jiang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Efficient mapping of table pipelines for software-defined networkin...
- Patent number 9,674,081
- Issue date Jun 6, 2017
- Xilinx, Inc.
- Weirong Jiang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Modular and scalable cyclic redundancy check computation circuit
- Patent number 9,350,385
- Issue date May 24, 2016
- Xilinx, Inc.
- Weirong Jiang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
RAM-based ternary content addressable memory
- Patent number 9,111,615
- Issue date Aug 18, 2015
- Xilinx, Inc.
- Weirong Jiang
- G11 - INFORMATION STORAGE
Information Patent Grant
High throughput finite state machine
- Patent number 9,110,524
- Issue date Aug 18, 2015
- Xilinx, Inc.
- Weirong Jiang
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
MODULAR AND SCALABLE CYCLIC REDUNDANCY CHECK COMPUTATION CIRCUIT
- Publication number 20140281844
- Publication date Sep 18, 2014
- Xilinx, Inc.
- Weirong Jiang
- H03 - BASIC ELECTRONIC CIRCUITRY